DipSwitch
bd9b3a269c
cpu/stm32/perip/dac: Move DAC implementation to stm32_common/periph since all STM32 DAC's have the same basics
2016-03-29 22:25:50 +02:00
Hauke Petersen
46bf22a01d
cpu/stm32f3: adapted GPIO driver
2016-03-17 14:55:30 +01:00
DipSwitch
d72cdcaad2
cpu/stm32/gpio_exti: EXTI->PR is of type RW_w1 so don't RMW the pending status flags
2016-03-11 15:46:41 +01:00
DipSwitch
df996044e2
STM32 GPIO: Fix exti_isr handling to only call callbacks of lines with have there interrupt enabled
2016-02-21 09:43:42 +01:00
Hauke Petersen
ad0abdcadd
cpus: use default isr_ctx struct in GPIO drivers
2016-01-27 17:00:37 +01:00
Hauke Petersen
32cf5423a2
cpu/stm32f3: disable debug in GPIO driver
2015-09-07 18:13:00 +02:00
Hauke Petersen
ad0e9c26b6
cpu/stm32f3: fixed init_af in GPIO driver
2015-06-15 20:40:40 +02:00
Hauke Petersen
3a2d89f88d
cpu/stm32f3: remodeled GPIO driver implementation
2015-06-12 19:10:48 +02:00
d0dfbf0079
cpu: stm32f3: periph: gpio: fix possibly uninitialized variable access
2015-04-08 19:52:14 +02:00
8653e685bc
stm32f3: gpio: fix isr2
2015-04-08 19:52:14 +02:00
Hauke Petersen
e7fbaf3815
cpu: removed NAKED attribute from ISRs
...
- removed the __attribute__((naked)) from ISRs
- removed ISR_ENTER() and ISR_EXIT() macros
Rationale: Cortex-Mx MCUs save registers R0-R4 automatically
on calling ISRs. The naked attribute tells the compiler not
to save any other registers. This is fine, as long as the
code in the ISR is not nested. If nested, it will use also
R4 and R5, which will then lead to currupted registers on
exit of the ISR. Removing the naked will fix this.
2014-10-30 19:33:32 +01:00
Hauke Petersen
13894fa70c
cpus: adjusted uart implementations for changed IF
...
- adjusted stm32f0
- adjusted stm32f3
- adjusted stm32f4
- adjusted sam3x8e
- adjusted nrf51822
2014-08-15 12:23:39 +02:00
Hauke Petersen
c5c860f435
cpu: Initial import of stm32f3
2014-07-31 19:38:26 +02:00
