This is a rewrite of the Kinetis GPIO driver which follows the
refactored API in [1]. Pins are specified using the GPIO_PIN(PORT_x, y)
macro, e.g. GPIO_PIN(PORT_E, 25) for the PTE25 pin.
The interrupt pin handling is now implemented as a linked list, this
is more memory efficient, but with a minor variation in interrupt
latency depending on in what order the pins were initialized at
runtime.
Because the linked list entries are taken from a shared pool, there is
also the possibility of running out of available configuration slots,
define the preprocessor macro GPIO_INT_POOL_SIZE in periph_conf.h if
you need more than 16 pins configured for interrupts in the same
application.
[1]: https://github.com/RIOT-OS/RIOT/pull/3095
e4218: SIM/FLEXBUS: SIM_SCGC7[FLEXBUS] bit should be cleared when the
FlexBus is not being used.
Errata type: Errata
Description:
The SIM_SCGC7[FLEXBUS] bit is set by default. This means that the
FlexBus will be enabled and come up in global chip select mode. With
some code sequence and register value combinations the core could
attempt to prefetch from the FlexBus even though it might not actually
use the value it prefetched. In the case where the FlexBus is
unconfigured, this can result in a hung bus cycle on the FlexBus.
Workaround:
- If the FlexBus is not being used, disabled the clock to the FlexBus
during chip initialization by clearing the SIM_SCGC7[FLEXBUS] bit.
- If the FlexBus will be used, then enable at least one chip select as
early in the chip initialization process as possible.
- Merged the two kinetis_common ldscripts into a single script.
- Updated cpus to use the new script
- Updated K60 to merge sram_l and sram_u into one segment
- Use BITBAND_REG32 instead of BITBAND_REG for improved code readability.
- Remove BITBAND_PERIPH* from cpu-conf.h
- Remove BITBAND_REG from MK60D10.h, MK60DZ10.h
As discussed in #2725, this commit renames a number of stacksize constants to
better convey their intended usage. In addition, constants for thread priority
are given a `THREAD_` prefix. Changes are:
* KERNEL_CONF_STACKSIZE_PRINTF renamed to THREAD_EXTRA_STACKSIZE_PRINTF
* KERNEL_CONF_STACKSIZE_DEFAULT renamed to THREAD_STACKSIZE_DEFAULT
* KERNEL_CONF_STACKSIZE_IDLE renamed to THREAD_STACKSIZE_IDLE
* KERNEL_CONF_STACKSIZE_MAIN renamed to THREAD_STACKSIZE_MAIN
* Move thread stacksizes from kernel.h to thread.h, since the prefix changed
* PRIORITY_MIN renamed to THREAD_PRIORITY_MIN
* PRIORITY_IDLE renamed to THREAD_PRIORITY_IDLE
* PRIORITY_MAIN renamed to THREAD_PRIORITY_MAIN
* Move thread priorities from kernel.h to thread.h since the prefix has changed
* MINIMUM_STACK_SIZE renamed to THREAD_STACKSIZE_MINIMUM for consistency
Tested on the following Freescale Kinetis K60 CPUs:
- MK60DN512VLL10
The port should with a high probability also support the following variations of the above CPUs (untested):
- MK60DN256VLL10
And possibly also:
- MK60DX256VLL10
- MK60DX512VLL10
- MK60DN512VLQ10
- MK60DN256VLQ10
- MK60DX256VLQ10
- MK60DN512VMC10
- MK60DN256VMC10
- MK60DX256VMC10
- MK60DN512VMD10
- MK60DX256VMD10
- MK60DN256VMD10
Currently not working on the following CPUs (Missing PIT channel
chaining necessary for kinetis_common/periph/timer implementation):
- MK60DN256ZVLL10
- MK60DN512ZVLL10
- MK60DX256ZVLL10
- MK60DX512ZVLL10
- MK60DN512ZVLQ10
- MK60DN256ZVLQ10
- MK60DX256ZVLQ10
- MK60DN512ZVMC10
- MK60DN256ZVMC10
- MK60DX256ZVMC10
- MK60DN512ZVMD10
- MK60DX256ZVMD10
- MK60DN256ZVMD10
Regarding header files from Freescale:
dist/tools/licenses: Add Freescale CMSIS PAL license pattern
Redistribution is OK according to:
https://community.freescale.com/message/477976?et=watches.email.thread#477976
Archive copy in case the above link disappears:
https://web.archive.org/web/20150328073057/https://community.freescale.com/message/477976?et=watches.email.thread
Applies to:
- MK60DZ10.h (K60 variant)
