If the INT pin is initialized if the callback function parameter `cb` is `NULL`, the driver crashes the first time an interrupt is triggered. Therefore, the INT pin must be initialized only if also the callback function parameter `cb` is not `NULL`.
Even if the interrupt pin is not initialized here because the callback function parameter `cb` is NULL, the device interrupts are configured here so that they will work when the interrupt pin is initialized later, as is the case when the Touch Device API is used, for example. Since the interrupt state is cleared on each read, this is not a problem even if the interrupt pin is not used at all.
To be able to test the touch device in polling mode, variable `TOUCH_DEV_POLLING` is introduced. It is set to 0 by default and can be overriden by 1 to use the polling mode. The polling period can be controlled by the `TOUCH_DEV_POLLING_PERIOD` variable.
19863: pkg/flashdb: bump to 2.0.0 r=benpicco a=benpicco
19864: tests/gcoap_fileserver: add zep_dispatcher to TEST_DEPS r=benpicco a=benpicco
19865: tests/pkg/lvgl*: fix the main thread stack size for ESPs r=benpicco a=gschorcht
### Contribution description
ESPx SoC need more stack size for the main thread to avoid stack overflows.
### Testing procedure
Use any ESP32 board or any ESP32-S2 board and flash `tests/pkg/lvgl` for the `esp32-wrover-kit` respective the `esp32s2-lilygo-ttgo-t8`, for example:
```
BOARD=esp32-wrover-kit make -j8 -C tests/pkg/lvgl flash
```
Without this PR the application crashes
```
main(): This is RIOT! (Version: 2023.10-devel-106-gd512f-tests/pkg/lvgl_fix_main_stack_size)
EXCEPTION!! exccause=29 (StoreProhibitedCause) `@4008274a` excvaddr=fefffffb
heap: 310368 (used 4176, free 306192) [bytes]
register set
pc : 40082f74 ps : 00050033 exccause: 0000001d excvaddr: fefffffb
epc1 : 40082f74
a0 : 4008274a a1 : 3ffb1bd0 a2 : fefffff7 a3 : 00000000
a4 : 3ff000dc a5 : 400826e0 a6 : 00000000 a7 : 3ffb1e08
a8 : 0000000b a9 : 3ffb1df8 a10 : 3ffb1e7c a11 : 00000001
a12 : 00000000 a13 : 00000000 a14 : 00000000 a15 : 000000a3
```
with this PR the application works as expected.
### Issues/PRs references
19869: make: COMPILE_COMMANDS_PATH adapt for external apps r=benpicco a=kfessel
### Contribution description
`COMPILE_COMMANDS_PATH` currently defaults to `RIOTBASE` which may not be an parent path for external applications -> set to `APPDIR` in case
### Testing procedure
- current good will stay good
test with riot examples and or testes `$make compile-commands` should create a `compile_command.json` in `<RIOT>`
- test with external app Makefile including
`include $(RIOTBASE)/Makefile.include`
should create `compile_command.json` in `APPDIR`
### Issues/PRs references
Co-authored-by: Benjamin Valentin <benjamin.valentin@ml-pa.com>
Co-authored-by: Gunar Schorcht <gunar@schorcht.net>
Co-authored-by: Karl Fessel <karl.fessel@ml-pa.com>
19824: boards/sipeed_longan_nano: separate board definition for Sipeed Longan Nano TFT r=benpicco a=gschorcht
### Contribution description
This PR provides a minimal separate board definition for the Sipeed Longan Nano version with TFT display which is just an extension of `boards/sipeed-longan-nano` with enabled TFT display module.
From the lessons we had to learn with the Kconfig modelling of optional hardware, the TFT version of the Sipeed Longan Nano board has been split off into its own board definition based on the existing Siepeed Longan Nano board.
Commits ba29a5eefad6f24106d51bf4fbd0d1407bc7b816, 237819eac894399e423f24ffd9b79b48af1cf25c, 6d8b56dcd426580ddbbbecd003ece54d46cee05c and c5faf349d63aef28b3aa3cfce8250229b6622a15 are small cleanups of peripheral configurations and could be split from this PR as follow-up PR (changes +70 -36).
### Testing procedure
Green CI
```
BOARD=sipeed-longan-nano-tft make -j8 -C tests/drivers/st77xx flash
```
should work
### Issues/PRs references
Follow up to PR #19813 and PR #19814
Prerequisite for PR #19825 and PR #19827
19855: gnrc_static: fix static PID assignment r=benpicco a=benpicco
19862: cpu/riscv_common: remove picolibc from blacklisting in CI r=benpicco a=gschorcht
### Contribution description
`picolibc` is now supported by the RISC-V toolchain in `riotdocker`. It is not necessary to blacklist it in CI any longer.
Reference: `picolib` was blacklisted by commit 45270dada0 in PR #15011.
### Testing procedure
1. Green CI
2. Check feature list for CI compilation:
```
BUILD_IN_DOCKER=1 RIOT_CI_BUILD=1 FEATURES_OPTIONAL=picolibc \
BOARD=sipeed-longan-nano make -j8 -C tests/sys/shell info-modules | grep picolib
picolibc
picolibc_stdout_buffered
picolibc_syscalls_default
```
### Issues/PRs references
Co-authored-by: Gunar Schorcht <gunar@schorcht.net>
Co-authored-by: Benjamin Valentin <benjamin.valentin@bht-berlin.de>
After cleaning up the default config of SPI, this commit cleans up the configuration for `sipeed-longan-nano` a bit:
- PA4 is no longer used as default CS for `SPI_DEV(1)`
- At least one DAC channel PA4 is always available if DAC is used.
- PA4 is always available as ADC channel if DAC is not used.
- The order of ADC and DAC channels has been changed accordingly.
This commit includes the following cleanups:
- The macros `I2C_DEV_1_USED` and `SPI_DEV_1_USED` are now used with the values 0 and 1. This allows to enable but also to disable the second interface even if the board definition enables it by default.
- The second I2C device `I2C_DEV(1)` and the second SPI device `SPI_DEV(1)` are now disabled by default.
- The second SPI device `SPI_DEV(1)` now uses PB5 as default CS signal instead of PA4 to keep PA4 free for ADC or DAC even if `SPI_DEV(1)` is used, for example for the TFT display.
This commit introduces a separate board definition based on the `sipeed-longan-nano` board definition for the TFT version of the Sipeed Longan Nano board.
19856: tests/net/gcoap_fileserver: Fix failing nightlies r=benpicco a=MrKevinWeiss
### Contribution description
This test has been failing inconsistently in the nightlies and sometimes on unrelated PRs. I was able to reproduce it with murdock and as soon as I added some print statements to the test it went away. Since the issue is something to do with a failure when comparing 2 files after a node sends a file I am guessing that the comparison comes occasionally too fast and the file is not ready.
Maybe there is some more synchronization needed after a `ncput` but for now just adding a small sleep should prevent this issue.
### Testing procedure
Run murdock multiple times or try to get it failing on a local setup then apply the PR...
### Issues/PRs references
Co-authored-by: MrKevinWeiss <weiss.kevin604@gmail.com>
19854: cpu/esp_common: esp-wifi: drop assert(val) r=benpicco a=benpicco
19858: tests/drivers/shtcx: don't repeat last string on error r=benpicco a=benpicco
Co-authored-by: Benjamin Valentin <benjamin.valentin@bht-berlin.de>
Co-authored-by: Benjamin Valentin <benjamin.valentin@ml-pa.com>
19452: dist/tools/esptools: upgrade ESP32x toolchains to GCC version 12.2 r=MrKevinWeiss a=gschorcht
### Contribution description
This PR upgrades ESP32x toolchains to GCC version 12.2 which is a prerequisite for upgrading the ESP-IDF to version 5.1.
This PR depends on PR #19450
### Testing procedure
`dist/tools/install.sh all` should install all ESP32x toolchains.
`. dist/tools/export.sh all` should make them visible.
### Issues/PRs references
Depends on PR #19450
Co-authored-by: Gunar Schorcht <gunar@schorcht.net>
19852: clang floating point handling fix r=MrKevinWeiss a=MrKevinWeiss
### Contribution description
As promised (with a delay for vacation), here is the nightlies fix. It is very easy...
I guess previously native had different handling of floating points (similar to cross-compiled gcc) when using clang. thanks to `@maribu` great work on fixing the llvm toolchain issues, that seems to not be an issue anymore (though I don't know the commit that fixed it).
Thus we remove clang conditions and enjoy a green CI.
### Testing procedure
It seems like this wasn't tested or doesn't get tested in the normal murdock/bors procedure (still don't know why) but can be easily verified with a/b testing (master vs this PR)
```
TOOLCHAIN=llvm make all test -C tests/pkg/cayenne-lpp/
```
and
```
TOOLCHAIN=llvm make all test -C tests/pkg/lora-serialization/
```
I also tested with cross compiling on the samr21 and they all work...
### Issues/PRs references
Look at nightlies...
Co-authored-by: MrKevinWeiss <weiss.kevin604@gmail.com>
19843: cpu/stm32/periph: add FMC/FSMC support for STM32 r=aabadie a=gschorcht
### Contribution description
The PR provides a driver for STM32 FMC/FSMC peripherals. It supports:
- NOR Flashes,
- PSRAMs/SRAMs,
- SDRAMs, and
- Display Controllers with MCU 8-/16-bit parallel interface.
NAND Flashes are not yet supported.
To use the FMC/FSMC, the `periph_fmc` module has to be enabled. To keep required data structures and resulting code as small as possible, a couple of pseudomodules are defined that have to be used in addition to the `periph_fmc` module to enable supported features. These are:
| Module | Feature |
|:-----------------------|:----------------------------------------|
| `periph_fmc_nor_sram` | enable NOR Flash and PSRAM/SRAM support |
| `periph_fmc_sdram` | enable SDRAM support |
| `periph_fmc_16bit` | enable 16-bit support |
| `periph_fmc_32bit` | enable 32-bit support |
The board has then to define
- the corresponding features according to the connected external device,
- the peripheral configuration of the FMC/FSMC of type `fmc_conf_t,`
- the configuration of the FMC banks which describe the connected external devices.
The PR includes the support for
- `stm32f429i-disc1` with 8 MByte SDRAM
- `stm32f746g-disco` with 16 MByte SDRAM
- `stm32l496g-disco` with 1 MByte SRAM
- `stm32f723e-disco` with 1 MByte SRAM.
To use the RAM connected to the FMC as heap, the board defines `FMC_RAM_ADDR` and ` FMC_RAM_LEN`. For that purpose:
- the linker symbols `_fmc_ram_addr` and `_fmc_ram_len` are set,
- a memory region `fcmram` is added in linker script for the FMC RAM based on these `_fcm_ram_*` linker symbols
- a section for the FMC RAM is defined in this memory region that defines the heap by setting `_sheap3` and `_eheap3` and
- the number of heaps is set to 4 to use `_sheap3` and `_eheap3` even though `_sheap1` and `_eheap1` (the backup RAM) and `_sheap2` and `_eheap2` (SRAM4) are not present.
Once the `drivers/st77xx` and `drivers/lcd` changes are merged, the display for boards like
the `stm32l496g-disco` and `stm32f723e-disco` can also use the FMC peripheral.
~**NOTE**: The PR includes the fix in PR #19842 for now (commit 560fea17a0c50483214770855e22cc94df0e55b5).~
### Testing procedure
1. Use one of the boards above and flash `tests/driver/stm32_fmc`, for example:
```
BOARD=stm32f429i-disc1 make -j8 -C tests/drivers/stm32_fmc flash test
```
The test should succeed.
**NOTE**: There is still a problem with `stm32f746g-disco`. It crashes with a hard-fault on accessing the upper 8 MByte of the 16 MByte.
2. Use the board above and flash `tests/sys/malloc`, for example:
```
USEMODULE=periph_fmc CFLAGS='-DCHUNK_SIZE=4096 -DDEBUG_ASSERT_VERBOSE' \
BOARD=stm32f429i-disc1 make -j8 -C tests/sys/malloc
```
The FMC RAM should be used for `malloc`. On `stm32f746g-disco` for example
```
...
Allocated 4096 Bytes at 0x2002d7c8, total 184672
Allocated 4096 Bytes at 0x2002e7e0, total 188776
Allocated 4096 Bytes at 0xd0000008, total 192880
Allocated 4096 Bytes at 0xd0001010, total 196984
Allocated 4096 Bytes at 0xd0002018, total 201088
...
Allocated 4096 Bytes at 0xd07fd6d0, total 8544520
Allocated 4096 Bytes at 0xd07fe6e8, total 8548624
Allocations count: 2083
```
### Issues/PRs references
~Depends on PR #19842~
19847: .github: drop test-on-ryot workflow r=aabadie a=aabadie
Co-authored-by: Gunar Schorcht <gunar@schorcht.net>
Co-authored-by: Alexandre Abadie <alexandre.abadie@inria.fr>
To detect misconfigurations of addresses and sizes, the whole memory is filled word-wise with it's addresses. If the content doesn't match, it prints the address and the content.
f
