Add periph_uart_nonblocking. Since cc2538 has a transmit FIFO write
to the FIFO first and to a tsrb buffer only when the transmit FIFO
is full.
Rely on the FIFO TXIFLSEL condition to fill up FIFO as space becomes
available.
This commit adds the periph_uart_mode USEMODULE
It implements all functionality defined in the common uart driver
This means all parity modes, data bits, and stop bits
Changed the style of the UART configuration for different boards,
from a define based configuration to one based on an array of
structs, one struct for each UART, with the format of the struct defined
in cc2538/include/periph_cpu.h.
- Defined the fields of the struct in periph_cpu.h
- Removed the compilation includes that were in uart.c for each UART
- Implemented a generic ISR subroutine for clarity
- combined uart_base and uart_init in uart.c
- used bitmask for the interrupt setup
- took the uart Rx, Tx, and IRQ numbers out of the config
(as this has to match the .dev field). Replaced with
macros from the uart number
- took out some unused code
- implemented power on/off commands
- removed reset function - now bytes are just discarded on error
- Rx now not initialised if Rx callback = NULL, as per
drivers/periph/uart.h
- device is now enabled after callbacks are set, not before
- asserts raised if rts and cts are enabled for UART0
- BIT macro removed
- removed the __attribute__((naked)) from ISRs
- removed ISR_ENTER() and ISR_EXIT() macros
Rationale: Cortex-Mx MCUs save registers R0-R4 automatically
on calling ISRs. The naked attribute tells the compiler not
to save any other registers. This is fine, as long as the
code in the ISR is not nested. If nested, it will use also
R4 and R5, which will then lead to currupted registers on
exit of the ISR. Removing the naked will fix this.
