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12 Commits

Author SHA1 Message Date
Benjamin Valentin
cfe606b601 cpu/lpc2387: gpio: Don't discriminate between rising & falling pins
The `test_irq()` function does not discriminate between rising and
falling pins, so there is no need to handle them separately.
2020-04-12 21:31:42 +02:00
Benjamin Valentin
6233175f16 cpu/lpc2387: gpio: Fix interrupts on PORT2
The calculation of `_state_index` is broken for `port = 2`

    _gpio_isr_map[n + (port<<1)];

Will not yield the right result. As a consequence, IRQs on Port 2
are not working.
The right thing here would be

    _gpio_isr_map[n + (port ? 32 : 0)];

But we might just re-using the `_isr_map_entry()` function.
Also only iterate as many times as there are set interrupt bits.
2020-04-12 21:31:42 +02:00
Martine Lenders
0ed57df4b5 lpc2387: mark closing #endif for MODULE_PERIPH_GPIO_IRQ 2018-10-09 15:11:00 +02:00
Hauke Petersen
72986ecb9b cpu/lpc2387/gpio: use gpio_irq feature 2018-09-21 08:19:15 +02:00
Marian Buschsieweke
1d0f90dcdf
cpu/lpc2387: Various fixes for GPIO driver
- Fixed documentation
- Use bitwise operation instead of multiplication and addition in `GPIO_PIN()`
- Allow GPIOs to be configured as input via `gpio_init()`
- Fixed bugs in `gpio_init_mux`:
    - `0x01 << ((pin & 31) * 2)` was used before to generate the bitmask, but
      this would shift by 62 to the left. Correct is `0x01 << ((pin & 15) * 2)`
      (See [datasheet](https://www.nxp.com/docs/en/user-guide/UM10211.pdf) at
      pages 156ff)
    - Only one of the two bits was cleared previously
- Changed strategy to access GPIO pins:
    - Previous strategy:
        - Set all bits in FIOMASK except the one for the pin to control to
          disable access to them
        - Set/clear/read all pins in the target GPIO port (but access to all but
          the target pin is ignored because of the applied FIOMASK)
    - New strategy:
        - Set/clear/read only the target pin
    - Advantages:
        - Only one access to a GPIO register instead of two
        - Proven approach: Access to GPIOs on lpc2387 is mostly done by
          accessing the GPIO registers directy (e.g. see the sht11 driver).
          Those accesses never touch the FIOMASK register
        - No unwanted side effects: Disabling all but one pin in a GPIO port
          without undoing that seems not to be a good idea
2018-06-18 09:10:25 +02:00
smlng
692cf96297 doc: fix doxygen grouping of cpu periph drivers 2017-06-26 14:42:11 +02:00
DipSwitch
0bb4748a94 core: Fix/refactor function naming in core/incude/irq.h 2016-03-20 16:47:34 +01:00
Hauke Petersen
877d06bda8 cpu/lpc2387: adapted GPIO driver 2016-03-17 14:39:11 +01:00
Hauke Petersen
ad0abdcadd cpus: use default isr_ctx struct in GPIO drivers 2016-01-27 17:00:37 +01:00
Oleg Hahm
d92ec1d11e lpc2387: fix pedantic compiler warnings 2015-12-07 20:28:53 +01:00
Oleg Hahm
49917a5797 core: cpu: fix check for DEVELHELP 2015-09-12 12:43:15 +02:00
3c5f31eb95 cpu: lpc2387: add periph/gpio imlementation 2015-08-14 16:50:41 +02:00