3 Commits

Author	SHA1	Message	Date
kenrabold	1d6e37a7f7	cpu/fe310: interrupt handling cleanup ... Cleanup of FE310 interrupt handler code Optimization of intr context frame Reduce size of intr stack Added unhandled trap output Fix PR #12237	2019-09-27 13:32:43 -07:00
kenrabold	97d1dc0821	cpu/fe310: Add support for FE310_G002 ... Added support for FE310_G002 CPU variant that is on new HiFive1B board	2019-07-19 13:25:17 -07:00
kenrabold	7d1d5e77d8	cpu/fe310: add RISC-V cpu FE310 ... New CPU FE310 from SiFive based on RISC-V architecture build: add makefile for RISC-V builds Makefile for builds using RISC-V tools	2018-05-29 15:21:45 -07:00