The `Makefile.ci` was intended to be read and generated by command
line utilities and the contents should look exactly like this:
```
BOARD_INSUFFICIENT_MEMORY += \
board_a \
board_b \
... \
#
```
No fancy schmancy, no `include`, no nothing. This fixes the format.
When it is difficult to navigate a function, it is overdue to split
it up :D
Also, no need to test for feature `gpio_ll_irq` in `test_irq()` *and*
before calling `test_irq()`.
The documentation on the state `GPIO_DISCONNECT` was a bit vague. The
API doc said it should disconnect the GPIO from all peripherals, the
test also tested them for being electrically disconnected.
The documentation in both the test and the API is extended to point out
that a GPIO indeed SHOULD be in high impedance state, but that user
MUST NOT expect that this requested is honored by every implementation
and for every GPIO pin.
In the test it is also pointed out that failing the test for a GPIO
in the `GPIO_DISCONNECT` state being electrically disconnected is for
some pins expected, and that the test should be just run again with
different GPIOs. The test intentionally tests for a feature not provided
by every GPIO pin rather than warning on a failure: The effort to just
flash and run the test again with different GPIOs is relatively low, but
it does confirm correct behavior of the API.
When using level triggered IRQs, a new IRQ flag may already have been
set while the IRQ callback is executed. Hence, we cannot just toggle
the output, but rather should drive it low/high for a level trigger on
high/low.
Also test `gpio_ll_query_conf()` for the disconnected state as well.
The default pin config is only a place holder anyway. But if it is
invalid at least on AVR most of the firmware is considered unreachable.
This updates the default GPIO config to something that should look
plausible to the compiler for all MCUs supporting GPIO LL, so that
ROM and RAM size in the CI start making sense.
Printing the newline after the state was printed is not optional.
This also moves the call to `gpio_ll_print_conf()` and `puts("")` to
a static function to safe enough ROM so that this still can be flashed
on `nucleo-l011k4`.
Also the LF is display inside the [...].
Now it is more obvious what characters came in on the RX port of the UART.
Here is an example:
2024-01-20 20:57:41,368 # send 1 ati
2024-01-20 20:57:41,368 # UART_DEV(1) TX: ati
> 2024-01-20 20:57:41,393 # Success: UART_DEV(1) RX: [ati\r\r\n]
2024-01-20 20:57:41,398 # Success: UART_DEV(1) RX: [SARA-N310-00X-00\r\n]
2024-01-20 20:57:41,399 # Success: UART_DEV(1) RX: [\r\n]
2024-01-20 20:57:41,399 # Success: UART_DEV(1) RX: [OK\r\n]
This application uses `soft_uart` to bit-bang the name of a number of
configured GPIO pins via said pins at 9600 Bd. This way attaching an
USB UART bridge to one pin at a time easily reveals which MCU GPIO
pin a given pin on a board corresponds to. This is useful when no
schematic and no silkscreen labeling is available, or when the
information is misleading or outright incorrect (looking at the
E180-ZG120B-TB).
- the timeout computation for the spurious IRQ test confused numerator
and denominator in a fraction
- the timeout offset between timer channels was hardcoded to 5000 from
when the timer was only tested with 1 MHz as frequency
- This resulted in slooooow test runs when running at slow
frequencies
- fix overflow handling in the spinning wait
- likely this would never overflow anyway assuming that
`timer_init()` resets the counter value, but let's not rely on
this and just fix the bug for good
If the feature periph_timer_query_freqs is provided, use the
corresponding function to iterate over all supported frequencies to
increase test coverage.
- Detect when the same timer is used by `ztimer` (pulled in as
dependency for a peripheral driver, e.g. `periph_adc` on STM32F3) and
the test application
- Try to provide a better default (e.g. `TIMER_DEV(1)` when
`ztimer_periph_timer` is in use, `TIMER_DEV(0)` otherwise)
The R-2R resistor ladder dac --> ADC test was disabled due to a bug in
the v0.1 version of the shield. Since this has been fixed in v0.2 and
v0.3 of the shield, it can be re-enabled.
The comment regarding the high accuracy of the resistor is dropped, as
v0.3 has been ordered with cost efficient resistors rather than with
accurate ones. As a result, the tolerance for error has been increased
to 10%. This quite a bit more lax than I have hoped for, but false
positives would be something to avoid.
- fix a copy-paste error (`TIMER_FREQ_UART_TEST` was used in the SPI
test, but that should be `TIMER_FREQ_SPI_TEST`)
- use 400 kHz as slow SPI frequency, as faster STM32 MCUs just cannot
divide the APB clock down to 100 kHz
- when detailed output is enabled, print the SPI clock in addition to
the SPI mode to ease figuring out what went wrong
- only have one `FAILURE` message for a too fast byte transfer per
check, rather than per transmitted byte, to reduce the noise
- work around a bug of `periph_timer` on STM32 by reducing the clock
speed of the timer for the SPI test
The test should execute only with `make test-with-config` and not with
`make test`, as boards without the shield cannot pass the test.
For some reason I accidentally added both variants, which makes no
sense. This drops the `make test` variant.
Finally, the `README.md` is updated to refer to `make test-with-config`
instead of `make test`.
This test application makes use of the RIOT Peripheral Selftest Shield,
which connects e.g. PWM to ADC or SPI MOSI to SPI MISO, UART TXD to RXD,
etc. This provides quick and fully automated self testing capabilities.
Please note that the simplicity and ease of use of the hardware comes
with a prices: There are whole classes of issues that cannot be detected
automatically. This test cannot replace other testing approaches
(such as manual testing or PHiLIP on the HiL), but only complement them.
