8 Commits

Author	SHA1	Message	Date
Martine Lenders	769bf572a0	fe310: mark closing #endif for MODULE_PERIPH_GPIO_IRQ	2018-10-09 15:11:00 +02:00
Martine Lenders	4e92c2a424	Merge pull request #10007 from haukepetersen/fix_gpioirq_fe310 ... cpu/fe310/gpio: use gpio_irq feature	2018-10-09 14:22:43 +02:00
smlng	59e299635b	cppcheck: add/correct reason for cppcheck-suppress ... Adding and correcting description/rational on why certain cppcheck warnings or errors are intentionally suppressed.	2018-09-25 12:03:58 +02:00
Hauke Petersen	be94b99eda	cpu/fe310/gpio: use gpio_irq feature	2018-09-21 08:18:14 +02:00
smlng	740eafe93b	cpu/fe310: add missing PERIPH_TIMER_PROVIDES_SET	2018-09-07 22:15:13 +02:00
Hauke Petersen	c2184f3454	boards/cpu/drivers/sys: use generic stdio_ if	2018-08-22 10:54:25 +02:00
kenrabold	db4d67c4fd	make: add hifive1 to BOARD_INSUFFICIENT_MEMORY ... Added HiFive1 to BOARD_INSUFFICIENT_MEMORY list for examples and tests that are too big to fit build: fixed missing syscall and cpuid failures Added missing syscall stubs for nanostubs and fixed compile error with cpuid periph build: fixed whitespace error build: add hifive1 to more BOARD_INSUFFICIENT_MEMORY doc: fixed doxygen warnings Addressed Doxygen warnings in source file comments doc: more doxygen fixes doc: even more doxygen fixes doc: more changes build: fix pedantic and rdci_simple build failures make: exclude lua	2018-05-29 16:27:53 -07:00
kenrabold	7d1d5e77d8	cpu/fe310: add RISC-V cpu FE310 ... New CPU FE310 from SiFive based on RISC-V architecture build: add makefile for RISC-V builds Makefile for builds using RISC-V tools	2018-05-29 15:21:45 -07:00