Refactor cortexm_init to allow bits and pieces of
it to be called separately, while retaining the
current API, too. Needed for non-standard
Cortex-M initialisation, such as with nRF52
SoftDevice.
This Patch makes gpio_init precalculate the pin mask once,
This Patch makes gpio_init of atmega_common configure the pin as an input and configure the pullup in the case of GPIO_IN_PU.
GPIO_IN_PU and GPIO_IN need to change pullup so they need to change output (this is coverd by the not touching outputs is not guaranteed statement)
(this is a special case for atmega the pull_up is configured by writing 1 to the port_register which is also the level of the output if the pin is configured to output).
This fix makes it more compliant to comments in periph/gpio.h
- Previous cast was to a function pointer was not legal
- Using already present function pointer to store the IAP entry point to improve
readability. (Which also fixes the cast issue.)
- arm_reset was completely undocumented, even though technical details buried
deeply in the data sheet of the LPC2387 are involved in the code
- The attribute "naked" is misplaced, it should only be used when no C code
is present. However, the function consists of C code only
- The attribute "noreturn" has to be used in the declaration [1] of a function,
not in the implementation. Otherwise the caller is not informed and code using
the function will not be optimized.
[1]: https://gcc.gnu.org/onlinedocs/gcc/Common-Function-Attributes.html
Allow defining a specific rom length to use for linking the firmware,
_fw_rom_length, instead of the default configuration to use the whole rom from
_rom_offset to the end.
* Add cortexm_common/Makefile.include FW_ROM_SIZE configuration
* Add an assertion that _fw_rom_length still respects _rom_length
Define _rom_offset with a conditional evaluated at execution time to allow
setting it in compilation rules and generate in the same make instance different
elf files with different configurations.
Rework SPI periph driver to use proper RIOT GPIO API functions.
Also cleanup header files by using vendor defines and remove
obsolete code. Further, adapt board config accordingly.
The SPI bus frequency/clock is calculated relative to the MCUs
core clock. Currently all boards use the default 32MHz, hence
prescaler settings for SPI are all the same. This PR moves the
default config for 32MHz to the CPU and allows to be overriden
by board config if needed.
Remove unused or obsolete defines in headers, due to usage of
vendor headers. Also remove register bit definition in timer
struct because they where not used in the implementation.
This came up when compiling an application for an NRF5x-based board
with LLVM/clang. The function does not seem to be used throughout the
file so I just removed it.
