`thread_measure_stack_free()` previously assumed that reading past the
stack is safe. When the stack was indeed part of a thread, the
`thread_t` structure is put after the stack, increasing the odds of
this assumption to hold. However, `thread_measure_stack_free()` could
also be used on the ISR stack, which may be allocated at the end of
SRAM.
A second parameter had to be added to indicate the stack size, so that
reading past the stack can now be prevented.
This also makes valgrind happy on `native`/`native64`.
We occasionally have some public `foo.h` header that includes a private
`foo_arch.h` header. Users are expected to include the `foo.h` header
and not the `foo_arch.h`. However, clangd will claim that the `#include`
of `foo.h` is unused if only functions / macros/ types / ... from
`foor_arch.h` is used and nothing from `foo.h`.
This adds the `IWYU pragma: export` comment to the include of
`foo_arch.h` in `foo.h`, so that clangd treats functions / macros /
types provided by `foo_arch.h` as if they were instead provided by
`foo.h`, which fixes the false positives.
This patch adds calls to be able to peek at items other than just the
oldest item in a cib based FIFO. It also adds an "unsafe" peek to match
the existing "unsafe" put and get functions.
Adds a separate board for native64 instead of the `NATIVE_64BIT` workaround.
The files in `boards/native64` are more or less dummy files and just include
the `boards/native` logic (similar to `openlabs-kw41z-mini-256kib`).
The main logic for native is in `makefiles/arch/native.inc.mk`, `cpu/native`
and `boards/native`.
The remaining changes concern the build system, and change native board checks
to native CPU checks to cover both boards.
* priority_queue_t: Replaced `-1U` literal with PRIORITY_QUEUE_DATA_SIGNALING define
* architecture.h: Added 64-bit
* bloom.h: Fixed typedef for the hashfp_t function pointer
* vfs.h: Increased default vfs buffer sizes for 64 bit
* bytes.h: Check if socklen_t is already defined
* ztimer: Use PRIxPTR format specifier
Only minor changes are required to make the kernel 64 bit compatible.
Most of the changes are either DEBUG/printf formatting or different types for void pointer casting.
The only other change is the type of the `data` member in priority_queue_node_t, as `data` must be able to store a pointer.
For current architectures, the assumption `sizeof(unsigned int) == sizeof(void *)` holds, but not for 64 bit.
Therefore, the type is changed to `uintptr_t', which has the same size for the current architectures, but can also store a pointer in 64 bits.
19963: sys/event/timeout: add event_timeout_is_pending() r=benpicco a=benpicco
19971: sys/shell/gnrc_netif: Fix a few blockers for sharing ifconfig shell r=benpicco a=yarrick
19974: gnrc_ipv6_ext_frag: _completed: Add comment why list head is not checked for NULL pointer dereference r=benpicco a=miri64
19975: pkg/nanocbor: Bump to latest commit r=benpicco a=bergzand
### Contribution description
Not much to see here
Important changes:
- Add stream-like interface for encoder
- Separate functions for number of items left in arrays and maps
### Testing procedure
The usual test should still work
### Issues/PRs references
None
19976: core: Express -1 as ~0 in thread_status_t cast r=benpicco a=SimonIT
Co-authored-by: Benjamin Valentin <benjamin.valentin@ml-pa.com>
Co-authored-by: Erik Ekman <eekman@google.com>
Co-authored-by: Martine Lenders <m.lenders@fu-berlin.de>
Co-authored-by: Koen Zandberg <koen@bergzand.net>
Co-authored-by: SimonIT <simonit.orig@gmail.com>
19712: cpu/riscv: Add PMP driver r=MrKevinWeiss a=Teufelchen1
### Contribution description
Hi! 🐘
this adds a basic RISC-V physical memory protection (PMP) driver to RIOT. Well, 'driver' might be a stretched, feels more like a little utility :)
EDIT: Also added a no-execute RAM option for the hifive & a corresponding test
Since I only have an Hifive rev b, it's only enabled on this board / cpu. I also tested the code on an ESP32-C but the feature can't be enabled there, as `cpu/riscv_common/` is not used by the ESP32...
### Testing procedure
* Grab a hifive rev b
* go to `examples/hello-world`
* Add `USEMODULES += periph_pmp` to the `Makefile`
* Include `pmp.h` in `main.c`
* Add code e.g. `print_pmpcfg(0);`
* compile & flash & term
You should see something like this:
```
# Hello World!
# You are running RIOT on a(n) hifive1b board.
# This board features a(n) fe310 MCU.
# pmp00cfg: - R-X OFF 0x00000000 - 0x00000000
```
Co-authored-by: Teufelchen1 <bennet.blischke@outlook.com>
19618: cpu/stm32: fix riotboot settings for L4 and WB r=benpicco a=gschorcht
### Contribution description
This PR fixes the `riotboot` configuration for L4 and WB.
The family is not called `stm32l4` or `stm32wb` but `l4` and `wb`. That is, the `riotboot` configuration didn't work at all. Furthermore, a minimum `RIOTBOOT_LEN` of `0x2000` is required for L4.
Found when investigating the compilation errors for `bootloaders/riotboot_serial` in PR #19576.
### Testing procedure
1. Green CI.
2. Use the following commands:
```
BOARD=nucleo-l496zg make -C tests/riotboot info-debug-variable-RIOTBOOT_HDR_LEN
BOARD=p-nucleo-wb55 make -C tests/riotboot info-debug-variable-RIOTBOOT_HDR_LEN
```
In master these commands give
```
0x400
```
With this PR these commands give
```
0x200
```
as expected.
3. Use the following commands:
```
BOARD=nucleo-l496zg make -C tests/riotboot info-debug-variable-RIOTBOOT_LEN
BOARD=p-nucleo-wb55 make -C tests/riotboot info-debug-variable-RIOTBOOT_LEN
```
In master these commands give
```
0x1000
```
With this PR these commands give
```
0x2000
```
as expected.
### Issues/PRs references
19639: tests/net/gnrc_mac_timeout: add automated test r=aabadie a=aabadie
19644: gnrc_ipv6_nib: include RIO with all subnets in downstream RA r=benpicco a=benpicco
19649: gnrc_sixlowpan_iphc: prefix bits outside context must be zero r=benpicco a=benpicco
19656: gnrc/ipv6_auto_subnets: allow to configure minimal prefix length r=benpicco a=benpicco
Co-authored-by: Gunar Schorcht <gunar@schorcht.net>
Co-authored-by: Alexandre Abadie <alexandre.abadie@inria.fr>
Co-authored-by: Benjamin Valentin <benjamin.valentin@ml-pa.com>
