6 Commits

Author	SHA1	Message	Date
Koen Zandberg	2692957c0e	riscv_common: Refactor common fe310 code to riscv_common	2021-02-05 09:32:19 +01:00
Koen Zandberg	ba518ede09	cpu/fe310: Uncrustify code	2021-01-15 12:02:55 +01:00
Bas Stottelaar	22243aec7a	cpu/*: realign ENABLE_DEBUG	2020-10-23 00:46:26 +02:00
Koen Zandberg	bef82edf43	fe310: Adapt peripherals to use the plic driver	2020-08-31 16:26:43 +02:00
Francisco Molina	442b11d0ee	cpu/fe310: add unified rtt configuration	2020-08-12 14:46:59 +02:00
kenrabold	7d1d5e77d8	cpu/fe310: add RISC-V cpu FE310 ... New CPU FE310 from SiFive based on RISC-V architecture build: add makefile for RISC-V builds Makefile for builds using RISC-V tools	2018-05-29 15:21:45 -07:00