A dispatcher function is implemented for directing writes to the correct
function. The dispatcher is bypassed completely if the CPU only contain
one kind of UART module.
There are at least two different UART hardware modules deployed in
different Kinetis CPU families (or possibly three or more when counting
variations of the UART module). The UART module is an older 8 bit module
with advanced functionality, while the LPUART is a 32 bit module with
focus on low power consumption.
- The older families in the K series all have UART modules.
- The K22F family have both UART and LPUART modules in the same CPU.
- Older L series (e.g. KL25Z) have two variations of the UART module
- Newer L series (e.g. KL43Z) have LPUART modules, and sometimes
UART as well.
- Newer W series (KW41Z) have only LPUART
Unify cpu_init for all Kinetis CPUs to reduce code duplication.
Updated the MCG driver implementation to make the configuration easier.
Most clock settings are initialized by kinetis_mcg_init() called from
cpu_init. Board specific external clock source initialization
(FRDM-K64F, PhyNode) needs to be performed in board_init instead of
in cpu_init.
- use assert() for checking the line parameter
- use 'bit.h' for bitbanding
- simplified code a bit
- unified style of defifining the board configuration
- removed unused configurations form pba-d-01-kw2x and frdm-k64f
The new implementation uses a precalculated map of which mode to switch
to next if going from mode A to mode B. This simplifies the
implementation for moving between modes which are not direct neighbors.
See mcg.h documentation for a diagram of the state machine for the
clocking modes. Also found in the CPU reference manual of all Kinetis
CPUs, MCG chapter, MCG mode state diagram.
The ADC prescaler computation was broken and gave too high ADC clock for
module clocks slower than 32 MHz (the >32 MHz case is already handled
separately)
This patch fix the bug in _i2c_receive. The STOP signal should be
generated before the reading from the data register because the
receiving of the next byte will be initiated by reading
the data register (dev->D).
