From fd8ddd616137cff575e3635d34503a4ba97f96f3 Mon Sep 17 00:00:00 2001 From: Akshai M Date: Mon, 8 Mar 2021 01:00:00 +0100 Subject: [PATCH] boards: add nucleo-wl55jc Co-authored-by: Kevin "Tristate Tom" Weiss --- boards/common/stm32/include/cfg_timer_tim2.h | 2 +- boards/nucleo-wl55jc/Makefile | 4 + boards/nucleo-wl55jc/Makefile.dep | 3 + boards/nucleo-wl55jc/Makefile.features | 13 ++ boards/nucleo-wl55jc/Makefile.include | 2 + boards/nucleo-wl55jc/include/board.h | 78 +++++++++++ boards/nucleo-wl55jc/include/gpio_params.h | 78 +++++++++++ boards/nucleo-wl55jc/include/periph_conf.h | 131 ++++++++++++++++++ cpu/stm32/cpu_common.c | 5 +- ...ommon_lx_wb.h => cfg_clock_common_lx_wx.h} | 10 +- cpu/stm32/include/clk/clk_conf.h | 4 +- .../{l4l5wb => l4l5wx}/cfg_clock_default.h | 26 ++-- cpu/stm32/include/cpu_conf_stm32_common.h | 5 +- cpu/stm32/include/periph/wl/periph_cpu.h | 42 ++++++ cpu/stm32/include/periph_cpu.h | 6 +- cpu/stm32/periph/Makefile | 6 +- cpu/stm32/periph/gpio_all.c | 3 +- cpu/stm32/periph/pm.c | 9 +- cpu/stm32/stm32_info.mk | 2 +- cpu/stm32/stmclk/Makefile | 2 +- .../stmclk/{stmclk_l4wbwl.c => stmclk_l4wx.c} | 25 +++- 21 files changed, 419 insertions(+), 37 deletions(-) create mode 100644 boards/nucleo-wl55jc/Makefile create mode 100644 boards/nucleo-wl55jc/Makefile.dep create mode 100644 boards/nucleo-wl55jc/Makefile.features create mode 100644 boards/nucleo-wl55jc/Makefile.include create mode 100644 boards/nucleo-wl55jc/include/board.h create mode 100644 boards/nucleo-wl55jc/include/gpio_params.h create mode 100644 boards/nucleo-wl55jc/include/periph_conf.h rename cpu/stm32/include/clk/{cfg_clock_common_lx_wb.h => cfg_clock_common_lx_wx.h} (91%) rename cpu/stm32/include/clk/{l4l5wb => l4l5wx}/cfg_clock_default.h (88%) create mode 100644 cpu/stm32/include/periph/wl/periph_cpu.h rename cpu/stm32/stmclk/{stmclk_l4wbwl.c => stmclk_l4wx.c} (97%) diff --git a/boards/common/stm32/include/cfg_timer_tim2.h b/boards/common/stm32/include/cfg_timer_tim2.h index dee761f2fd..d7f6008c6f 100644 --- a/boards/common/stm32/include/cfg_timer_tim2.h +++ b/boards/common/stm32/include/cfg_timer_tim2.h @@ -38,7 +38,7 @@ static const timer_conf_t timer_config[] = { .max = 0xffffffff, #endif #if defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32WB) || \ - defined(CPU_FAM_STM32G4) + defined(CPU_FAM_STM32WL) || defined(CPU_FAM_STM32G4) .rcc_mask = RCC_APB1ENR1_TIM2EN, #elif CPU_FAM_STM32MP1 .rcc_mask = RCC_MC_APB1ENSETR_TIM2EN, diff --git a/boards/nucleo-wl55jc/Makefile b/boards/nucleo-wl55jc/Makefile new file mode 100644 index 0000000000..4dd17b1d0c --- /dev/null +++ b/boards/nucleo-wl55jc/Makefile @@ -0,0 +1,4 @@ +MODULE = board +DIRS = $(RIOTBOARD)/common/nucleo + +include $(RIOTBASE)/Makefile.base diff --git a/boards/nucleo-wl55jc/Makefile.dep b/boards/nucleo-wl55jc/Makefile.dep new file mode 100644 index 0000000000..f41bf0f86b --- /dev/null +++ b/boards/nucleo-wl55jc/Makefile.dep @@ -0,0 +1,3 @@ +FEATURES_REQUIRED += periph_lpuart + +include $(RIOTBOARD)/common/nucleo/Makefile.dep diff --git a/boards/nucleo-wl55jc/Makefile.features b/boards/nucleo-wl55jc/Makefile.features new file mode 100644 index 0000000000..ac87b8468a --- /dev/null +++ b/boards/nucleo-wl55jc/Makefile.features @@ -0,0 +1,13 @@ +CPU = stm32 +CPU_MODEL = stm32wl55jc + +# Put defined MCU peripherals here (in alphabetical order) +FEATURES_PROVIDED += periph_i2c +FEATURES_PROVIDED += periph_lpuart +FEATURES_PROVIDED += periph_rtt +FEATURES_PROVIDED += periph_spi +FEATURES_PROVIDED += periph_timer +FEATURES_PROVIDED += periph_uart + +# Put other features for this board (in alphabetical order) +FEATURES_PROVIDED += riotboot diff --git a/boards/nucleo-wl55jc/Makefile.include b/boards/nucleo-wl55jc/Makefile.include new file mode 100644 index 0000000000..8db8eaed90 --- /dev/null +++ b/boards/nucleo-wl55jc/Makefile.include @@ -0,0 +1,2 @@ +# load the common Makefile.include for Nucleo boards +include $(RIOTBOARD)/common/nucleo64/Makefile.include diff --git a/boards/nucleo-wl55jc/include/board.h b/boards/nucleo-wl55jc/include/board.h new file mode 100644 index 0000000000..862e41c48a --- /dev/null +++ b/boards/nucleo-wl55jc/include/board.h @@ -0,0 +1,78 @@ +/* + * Copyright (C) 2021 Freie Universität Berlin + * + * This file is subject to the terms and conditions of the GNU Lesser + * General Public License v2.1. See the file LICENSE in the top level + * directory for more details. + */ + +/** + * @ingroup boards_nucleo-wl55jc + * @{ + * + * @file + * @brief Pin definitions and board configuration options + * + * @author Akshai M + * @author Hauke Petersen + */ + +#ifndef BOARD_H +#define BOARD_H + +#include "board_nucleo.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @name LED pin definitions and handlers + * @{ + */ +#define LED0_PORT GPIOB +#define LED0_PIN GPIO_PIN(PORT_B, 15) +#define LED0_MASK (1 << 15) +#define LED0_ON (LED0_PORT->BSRR = LED0_MASK) +#define LED0_OFF (LED0_PORT->BSRR = (LED0_MASK << 16)) +#define LED0_TOGGLE (LED0_PORT->ODR ^= LED0_MASK) + +#define LED1_PORT GPIOB +#define LED1_PIN GPIO_PIN(PORT_B, 9) +#define LED1_MASK (1 << 9) +#define LED1_ON (LED0_PORT->BSRR = LED1_MASK) +#define LED1_OFF (LED0_PORT->BSRR = (LED1_MASK << 16)) +#define LED1_TOGGLE (LED0_PORT->ODR ^= LED1_MASK) + +#define LED2_PORT GPIOB +#define LED2_PIN GPIO_PIN(PORT_B, 11) +#define LED2_MASK (1 << 11) +#define LED2_ON (LED0_PORT->BSRR = LED2_MASK) +#define LED2_OFF (LED0_PORT->BSRR = (LED2_MASK << 16)) +#define LED2_TOGGLE (LED0_PORT->ODR ^= LED2_MASK) +/** @} */ + +/* nucleo-wl55jc always use LED0, as there is no dual use of its pin */ +#ifndef AUTO_INIT_LED0 +#define AUTO_INIT_LED0 +#endif +/** @} */ + +/** + * @name User button + * @{ + */ +#define BTN0_PIN GPIO_PIN(PORT_A, 0) +#define BTN0_MODE GPIO_IN_PU +#define BTN1_PIN GPIO_PIN(PORT_A, 1) +#define BTN1_MODE GPIO_IN_PU +#define BTN2_PIN GPIO_PIN(PORT_C, 6) +#define BTN2_MODE GPIO_IN_PU +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif /* BOARD_H */ +/** @} */ diff --git a/boards/nucleo-wl55jc/include/gpio_params.h b/boards/nucleo-wl55jc/include/gpio_params.h new file mode 100644 index 0000000000..f464422bb3 --- /dev/null +++ b/boards/nucleo-wl55jc/include/gpio_params.h @@ -0,0 +1,78 @@ +/* + * Copyright (C) 2021 Freie Universität Berlin + * + * This file is subject to the terms and conditions of the GNU Lesser + * General Public License v2.1. See the file LICENSE in the top level + * directory for more details. + */ + +/** + * @ingroup boards_nucleo-wl55jc + * @{ + * + * @file + * @brief Board specific configuration of direct mapped GPIOs + * + * @author Akshai M + * @author Hauke Petersen + * + */ + +#ifndef GPIO_PARAMS_H +#define GPIO_PARAMS_H + +#include "board.h" +#include "saul/periph.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief GPIO pin configuration + */ +static const saul_gpio_params_t saul_gpio_params[] = +{ +#ifdef AUTO_INIT_LED0 + { + .name = "LED(blue)", + .pin = LED0_PIN, + .mode = GPIO_OUT + }, +#endif + { + .name = "LED(green)", + .pin = LED1_PIN, + .mode = GPIO_OUT + }, + { + .name = "LED(red)", + .pin = LED2_PIN, + .mode = GPIO_OUT + }, + { + .name = "Button(B1 User)", + .pin = BTN0_PIN, + .mode = BTN0_MODE, + .flags = SAUL_GPIO_INVERTED, + }, + { + .name = "Button(B2 User)", + .pin = BTN1_PIN, + .mode = BTN1_MODE, + .flags = SAUL_GPIO_INVERTED, + }, + { + .name = "Button(B3 User)", + .pin = BTN2_PIN, + .mode = BTN2_MODE, + .flags = SAUL_GPIO_INVERTED, + }, +}; + +#ifdef __cplusplus +} +#endif + +#endif /* GPIO_PARAMS_H */ +/** @} */ diff --git a/boards/nucleo-wl55jc/include/periph_conf.h b/boards/nucleo-wl55jc/include/periph_conf.h new file mode 100644 index 0000000000..7dcc5c6e59 --- /dev/null +++ b/boards/nucleo-wl55jc/include/periph_conf.h @@ -0,0 +1,131 @@ +/* + * Copyright (C) 2021 Freie Universität Berlin + * + * This file is subject to the terms and conditions of the GNU Lesser + * General Public License v2.1. See the file LICENSE in the top level + * directory for more details. + */ + +/** + * @ingroup boards_nucleo-wl55jc + * @{ + * + * @file + * @brief Peripheral MCU configuration for the nucleo-wl55jc board + * + * @author Akshai M + * @author Hauke Petersen + * + */ + +#ifndef PERIPH_CONF_H +#define PERIPH_CONF_H + +/* Add specific clock configuration (HSE, LSE) for this board here */ +#ifndef CONFIG_BOARD_HAS_LSE +#define CONFIG_BOARD_HAS_LSE 1 +#endif + +/* This board provides a 32MHz HSE oscillator */ +#ifndef CONFIG_BOARD_HAS_HSE +#define CONFIG_BOARD_HAS_HSE 1 +#endif + +#define CLOCK_HSE MHZ(32) + +#include "periph_cpu.h" +#include "clk_conf.h" +#include "cfg_timer_tim2.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @name UART configuration + * @{ + */ +static const uart_conf_t uart_config[] = { + { + .dev = LPUART1, + .rcc_mask = RCC_APB1ENR2_LPUART1EN, + .rx_pin = GPIO_PIN(PORT_A, 3), + .tx_pin = GPIO_PIN(PORT_A, 2), + .rx_af = GPIO_AF8, + .tx_af = GPIO_AF8, + .bus = APB12, + .irqn = LPUART1_IRQn, + .type = STM32_LPUART, + .clk_src = 0, /* Use APB clock */ + }, + { + .dev = USART1, + .rcc_mask = RCC_APB2ENR_USART1EN, + .rx_pin = GPIO_PIN(PORT_B, 7), + .tx_pin = GPIO_PIN(PORT_B, 6), + .rx_af = GPIO_AF7, + .tx_af = GPIO_AF7, + .bus = APB2, + .irqn = USART1_IRQn, + .type = STM32_USART, + .clk_src = 0, /* Use APB clock */ + }, +}; + +#define UART_0_ISR (isr_lpuart1) +#define UART_1_ISR (isr_usart1) + +#define UART_NUMOF ARRAY_SIZE(uart_config) +/** @} */ +/** + * @name SPI configuration + * @{ + */ +static const spi_conf_t spi_config[] = { + { + .dev = SPI1, + .mosi_pin = GPIO_PIN(PORT_A, 7), + .miso_pin = GPIO_PIN(PORT_A, 6), + .sclk_pin = GPIO_PIN(PORT_A, 5), + .cs_pin = GPIO_UNDEF, + .mosi_af = GPIO_AF5, + .miso_af = GPIO_AF5, + .sclk_af = GPIO_AF5, + .cs_af = GPIO_AF5, + .rccmask = RCC_APB2ENR_SPI1EN, + .apbbus = APB2, + } +}; + +#define SPI_NUMOF ARRAY_SIZE(spi_config) +/** @} */ + +/** + * @name I2C configuration + * @{ + */ +static const i2c_conf_t i2c_config[] = { + { + .dev = I2C2, + .speed = I2C_SPEED_NORMAL, + .scl_pin = GPIO_PIN(PORT_A, 12), + .sda_pin = GPIO_PIN(PORT_A, 11), + .scl_af = GPIO_AF4, + .sda_af = GPIO_AF4, + .bus = APB1, + .rcc_mask = RCC_APB1ENR1_I2C2EN, + .irqn = I2C2_ER_IRQn, + } +}; + +#define I2C_1_ISR isr_i2c2_er + +#define I2C_NUMOF ARRAY_SIZE(i2c_config) +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif /* PERIPH_CONF_H */ +/** @} */ diff --git a/cpu/stm32/cpu_common.c b/cpu/stm32/cpu_common.c index 42c4bca7ba..0e85de875c 100644 --- a/cpu/stm32/cpu_common.c +++ b/cpu/stm32/cpu_common.c @@ -173,7 +173,8 @@ void periph_clk_dis(bus_t bus, uint32_t mask) break; #endif #if defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32WB) || \ - defined(CPU_FAM_STM32G4) || defined(CPU_FAM_STM32L5) + defined(CPU_FAM_STM32G4) || defined(CPU_FAM_STM32L5) || \ + defined(CPU_FAM_STM32WL) case APB12: RCC->APB1ENR2 &= ~(mask); break; @@ -197,7 +198,7 @@ void periph_clk_dis(bus_t bus, uint32_t mask) #elif defined(CPU_FAM_STM32F2) || defined(CPU_FAM_STM32F4) || \ defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32F7) || \ defined(CPU_FAM_STM32WB) || defined(CPU_FAM_STM32G4) || \ - defined(CPU_FAM_STM32L5) + defined(CPU_FAM_STM32L5) || defined(CPU_FAM_STM32WL) case AHB1: RCC->AHB1ENR &= ~(mask); break; diff --git a/cpu/stm32/include/clk/cfg_clock_common_lx_wb.h b/cpu/stm32/include/clk/cfg_clock_common_lx_wx.h similarity index 91% rename from cpu/stm32/include/clk/cfg_clock_common_lx_wb.h rename to cpu/stm32/include/clk/cfg_clock_common_lx_wx.h index 72533e3e83..a100cfb3f4 100644 --- a/cpu/stm32/include/clk/cfg_clock_common_lx_wb.h +++ b/cpu/stm32/include/clk/cfg_clock_common_lx_wx.h @@ -13,22 +13,22 @@ * @{ * * @file - * @brief Base STM32Lx/WB clock configuration + * @brief Base STM32Lx/Wx clock configuration * * @author Hauke Petersen * @author Vincent Dupont * @author Alexandre Abadie */ -#ifndef CLK_CFG_CLOCK_COMMON_LX_WB_H -#define CLK_CFG_CLOCK_COMMON_LX_WB_H +#ifndef CLK_CFG_CLOCK_COMMON_LX_WX_H +#define CLK_CFG_CLOCK_COMMON_LX_WX_H #ifdef __cplusplus extern "C" { #endif /** - * @name Clock system configuration (L0/L1/L4/L5/WB) + * @name Clock system configuration (L0/L1/L4/L5/WB/WL) * @{ */ /* Select the desired system clock source between PLL, HSE or HSI */ @@ -87,5 +87,5 @@ extern "C" { } #endif -#endif /* CLK_CFG_CLOCK_COMMON_LX_WB_H */ +#endif /* CLK_CFG_CLOCK_COMMON_LX_WX_H */ /** @} */ diff --git a/cpu/stm32/include/clk/clk_conf.h b/cpu/stm32/include/clk/clk_conf.h index 0aced1bbcd..28160d2fc6 100644 --- a/cpu/stm32/include/clk/clk_conf.h +++ b/cpu/stm32/include/clk/clk_conf.h @@ -30,7 +30,7 @@ #include "cfg_clock_common_fx_gx_mp1.h" #else /* CPU_FAM_STM32L0 || CPU_FAM_STM32L1 || CPU_FAM_STM32L4 || * CPU_FAM_STM32L5 || CPU_FAM_STM32WB */ -#include "cfg_clock_common_lx_wb.h" +#include "cfg_clock_common_lx_wx.h" #endif #if defined(CPU_FAM_STM32F0) || defined(CPU_FAM_STM32F1) || \ @@ -45,7 +45,7 @@ #include "l0l1/cfg_clock_default.h" #elif defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32L5) || \ defined(CPU_FAM_STM32WB) || defined(CPU_FAM_STM32WL) -#include "l4l5wb/cfg_clock_default.h" +#include "l4l5wx/cfg_clock_default.h" #elif defined(CPU_FAM_STM32MP1) #include "mp1/cfg_clock_default.h" #else diff --git a/cpu/stm32/include/clk/l4l5wb/cfg_clock_default.h b/cpu/stm32/include/clk/l4l5wx/cfg_clock_default.h similarity index 88% rename from cpu/stm32/include/clk/l4l5wb/cfg_clock_default.h rename to cpu/stm32/include/clk/l4l5wx/cfg_clock_default.h index 22bbb95f2d..b8652f3d4c 100644 --- a/cpu/stm32/include/clk/l4l5wb/cfg_clock_default.h +++ b/cpu/stm32/include/clk/l4l5wx/cfg_clock_default.h @@ -18,8 +18,8 @@ * @author Alexandre Abadie */ -#ifndef CLK_L4L5WB_CFG_CLOCK_DEFAULT_H -#define CLK_L4L5WB_CFG_CLOCK_DEFAULT_H +#ifndef CLK_L4L5WX_CFG_CLOCK_DEFAULT_H +#define CLK_L4L5WX_CFG_CLOCK_DEFAULT_H #ifdef __cplusplus extern "C" { @@ -73,7 +73,13 @@ extern "C" { #endif #ifndef CONFIG_CLOCK_PLL_N #if IS_ACTIVE(CONFIG_CLOCK_PLL_SRC_HSE) && (CLOCK_HSE == MHZ(32)) +/* For STM32WL, VCO output frequency ((PLL input clock frequency / PLLM ) x PLLN ) + must be between 96 and 344 MHz. PLLN can have values <=127 & >=6 */ +#if IS_ACTIVE(CPU_FAM_STM32WL) +#define CONFIG_CLOCK_PLL_N (12) +#else #define CONFIG_CLOCK_PLL_N (16) +#endif /* CPU_FAM_STM32WL */ #elif IS_ACTIVE(CONFIG_CLOCK_PLL_SRC_HSI) || \ (IS_ACTIVE(CONFIG_CLOCK_PLL_SRC_HSE) && (CLOCK_HSE == MHZ(16))) #define CONFIG_CLOCK_PLL_N (32) @@ -126,7 +132,9 @@ extern "C" { ((CLOCK_PLL_SRC / CONFIG_CLOCK_PLL_M) * CONFIG_CLOCK_PLL_N) / CONFIG_CLOCK_PLL_R /* Set max allowed sysclk */ -#if defined(CPU_FAM_STM32WB) +#if defined(CPU_FAM_STM32WL) +#define CLOCK_CORECLOCK_MAX MHZ(48) +#elif defined(CPU_FAM_STM32WB) #define CLOCK_CORECLOCK_MAX MHZ(64) #elif defined(CPU_FAM_STM32L5) #define CLOCK_CORECLOCK_MAX MHZ(110) @@ -141,7 +149,9 @@ extern "C" { #endif #if CLOCK_CORECLOCK > CLOCK_CORECLOCK_MAX -#if CLOCK_CORECLOCK_MAX == MHZ(64) +#if CLOCK_CORECLOCK_MAX == MHZ(48) +#error "SYSCLK cannot exceed 48MHz" +#elif CLOCK_CORECLOCK_MAX == MHZ(64) #error "SYSCLK cannot exceed 64MHz" #elif CLOCK_CORECLOCK_MAX == MHZ(80) #error "SYSCLK cannot exceed 80MHz" @@ -155,20 +165,20 @@ extern "C" { #endif /* CLOCK_CORECLOCK > CLOCK_CORECLOCK_MAX */ #endif /* CONFIG_USE_CLOCK_PLL */ -#define CLOCK_AHB CLOCK_CORECLOCK /* HCLK, max: 64/80/120MHz */ +#define CLOCK_AHB CLOCK_CORECLOCK /* HCLK, max: 48/64/80/120MHz */ #ifndef CONFIG_CLOCK_APB1_DIV #define CONFIG_CLOCK_APB1_DIV (4) #endif -#define CLOCK_APB1 (CLOCK_AHB / CONFIG_CLOCK_APB1_DIV) /* PCLK1, max: 64/80/120MHz */ +#define CLOCK_APB1 (CLOCK_AHB / CONFIG_CLOCK_APB1_DIV) /* PCLK1, max: 48/64/80/120MHz */ #ifndef CONFIG_CLOCK_APB2_DIV #define CONFIG_CLOCK_APB2_DIV (2) #endif -#define CLOCK_APB2 (CLOCK_AHB / CONFIG_CLOCK_APB2_DIV) /* PCLK1, max: 64/80/120MHz */ +#define CLOCK_APB2 (CLOCK_AHB / CONFIG_CLOCK_APB2_DIV) /* PCLK1, max: 48/64/80/120MHz */ #ifdef __cplusplus } #endif -#endif /* CLK_L4L5WB_CFG_CLOCK_DEFAULT_H */ +#endif /* CLK_L4L5WX_CFG_CLOCK_DEFAULT_H */ /** @} */ diff --git a/cpu/stm32/include/cpu_conf_stm32_common.h b/cpu/stm32/include/cpu_conf_stm32_common.h index 37b2917ccf..60ad25940f 100644 --- a/cpu/stm32/include/cpu_conf_stm32_common.h +++ b/cpu/stm32/include/cpu_conf_stm32_common.h @@ -31,7 +31,8 @@ extern "C" { defined(CPU_FAM_STM32F7) || defined(CPU_FAM_STM32L0) || \ defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32L4) || \ defined(CPU_FAM_STM32WB) || defined(CPU_FAM_STM32G4) || \ - defined(CPU_FAM_STM32G0) || defined(CPU_FAM_STM32L5) + defined(CPU_FAM_STM32G0) || defined(CPU_FAM_STM32L5) || \ + defined(CPU_FAM_STM32WL) /** * @brief Timing register settings @@ -42,7 +43,7 @@ static const i2c_timing_param_t timing_params[] = { #if defined(CPU_FAM_STM32F0) || defined(CPU_FAM_STM32F7) || \ defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32WB) || \ defined(CPU_FAM_STM32G4) || defined(CPU_FAM_STM32G0) || \ - defined(CPU_FAM_STM32L5) + defined(CPU_FAM_STM32L5) || defined(CPI_FAM_STM32WL) [ I2C_SPEED_NORMAL ] = { .presc = 0xB, .scll = 0x13, /* t_SCLL = 5.0us */ diff --git a/cpu/stm32/include/periph/wl/periph_cpu.h b/cpu/stm32/include/periph/wl/periph_cpu.h new file mode 100644 index 0000000000..c3ae86de89 --- /dev/null +++ b/cpu/stm32/include/periph/wl/periph_cpu.h @@ -0,0 +1,42 @@ +/* + * Copyright (C) 2021 Freie Universität Berlin + * + * This file is subject to the terms and conditions of the GNU Lesser + * General Public License v2.1. See the file LICENSE in the top level + * directory for more details. + */ + +/** + * @ingroup cpu_stm32 + * @{ + * + * @file + * @brief STM32WL CPU specific definitions for internal peripheral handling + * + * @author Akshai M + * + */ + +#ifndef PERIPH_WL_PERIPH_CPU_H +#define PERIPH_WL_PERIPH_CPU_H + +#ifdef __cplusplus +extern "C" { +#endif + +#ifndef DOXYGEN + +/** + * @brief Starting address of the ROM bootloader + * see application note AN2606 ( Table 143 : System memory) + */ +#define STM32_BOOTLOADER_ADDR (0x1FFF0000) + +#endif /* ndef DOXYGEN */ + +#ifdef __cplusplus +} +#endif + +#endif /* PERIPH_WL_PERIPH_CPU_H */ +/** @} */ diff --git a/cpu/stm32/include/periph_cpu.h b/cpu/stm32/include/periph_cpu.h index a6c2a2069f..a3caf8be85 100644 --- a/cpu/stm32/include/periph_cpu.h +++ b/cpu/stm32/include/periph_cpu.h @@ -52,6 +52,8 @@ #include "periph/l5/periph_cpu.h" #elif defined(CPU_FAM_STM32WB) #include "periph/wb/periph_cpu.h" +#elif defined(CPU_FAM_STM32WL) +#include "periph/wl/periph_cpu.h" #endif #ifdef __cplusplus @@ -738,7 +740,7 @@ typedef enum { defined(CPU_FAM_STM32F7) || defined(CPU_FAM_STM32L0) || \ defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32WB) || \ defined(CPU_FAM_STM32G4) || defined(CPU_FAM_STM32G0) || \ - defined(CPU_FAM_STM32L5) + defined(CPU_FAM_STM32L5) || defined(CPU_FAM_STM32WL) I2C_SPEED_FAST_PLUS, /**< fast plus mode: ~1Mbit/s */ #endif } i2c_speed_t; @@ -774,7 +776,7 @@ typedef struct { defined(CPU_FAM_STM32F7) || defined(CPU_FAM_STM32L0) || \ defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32WB) || \ defined(CPU_FAM_STM32G4) || defined(CPU_FAM_STM32G0) || \ - defined(CPU_FAM_STM32L5) + defined(CPU_FAM_STM32L5) || defined(CPU_FAM_STM32WL) /** * @brief Structure for I2C timing register settings * diff --git a/cpu/stm32/periph/Makefile b/cpu/stm32/periph/Makefile index 5184150cdd..83c291a1b2 100644 --- a/cpu/stm32/periph/Makefile +++ b/cpu/stm32/periph/Makefile @@ -2,10 +2,12 @@ MODULE = periph # Select the specific implementation for `periph_i2c` ifneq (,$(filter periph_i2c,$(USEMODULE))) - ifneq (,$(filter $(CPU_FAM),f0 f3 f7 g0 g4 l0 l4 l5 wb)) + ifneq (,$(filter $(CPU_FAM),f0 f3 f7 g0 g4 l0 l4 l5 wb wl)) SRC += i2c_1.c - else # f1/f2/f4/l1 + else ifneq (,$(filter $(CPU_FAM),f1 f2 f4 l1)) SRC += i2c_2.c + else + $(error STM32 series I2C implementation not found.) endif endif diff --git a/cpu/stm32/periph/gpio_all.c b/cpu/stm32/periph/gpio_all.c index d6c2a6f9a9..006898d9d8 100644 --- a/cpu/stm32/periph/gpio_all.c +++ b/cpu/stm32/periph/gpio_all.c @@ -238,7 +238,8 @@ int gpio_init_int(gpio_t pin, gpio_mode_t mode, gpio_flank_t flank, isr_ctx[pin_num].arg = arg; /* enable clock of the SYSCFG module for EXTI configuration */ -#if !defined(CPU_FAM_STM32WB) && !defined(CPU_FAM_STM32MP1) && !defined(CPU_FAM_STM32WL) +#if !defined(CPU_FAM_STM32WB) && !defined(CPU_FAM_STM32MP1) && \ + !defined(CPU_FAM_STM32WL) #ifdef CPU_FAM_STM32F0 periph_clk_en(APB2, RCC_APB2ENR_SYSCFGCOMPEN); #elif defined(CPU_FAM_STM32G0) diff --git a/cpu/stm32/periph/pm.c b/cpu/stm32/periph/pm.c index eefcf0cf81..055c4ec102 100644 --- a/cpu/stm32/periph/pm.c +++ b/cpu/stm32/periph/pm.c @@ -49,7 +49,8 @@ #elif defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32G4) || \ defined(CPU_FAM_STM32L5) #define PM_STOP_CONFIG (PWR_CR1_LPMS_STOP1) -#elif defined(CPU_FAM_STM32WB) || defined(CPU_FAM_STM32G0) || defined(CPU_FAM_STM32WL) +#elif defined(CPU_FAM_STM32WB) || defined(CPU_FAM_STM32G0) || \ + defined(CPU_FAM_STM32WL) #define PM_STOP_CONFIG (PWR_CR1_LPMS_0) #elif defined(CPU_FAM_STM32F7) #define PM_STOP_CONFIG (PWR_CR1_LPDS | PWR_CR1_FPDS | PWR_CR1_LPUDS) @@ -71,7 +72,8 @@ #elif defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32G4) || \ defined(CPU_FAM_STM32L5) #define PM_STANDBY_CONFIG (PWR_CR1_LPMS_STANDBY) -#elif defined(CPU_FAM_STM32WB) || defined(CPU_FAM_STM32G0) || defined(CPU_FAM_STM32WL) +#elif defined(CPU_FAM_STM32WB) || defined(CPU_FAM_STM32G0) || \ + defined(CPU_FAM_STM32WL) #define PM_STANDBY_CONFIG (PWR_CR1_LPMS_0 | PWR_CR1_LPMS_1) #elif defined(CPU_FAM_STM32F7) #define PM_STANDBY_CONFIG (PWR_CR1_PDDS | PWR_CR1_CSBF) @@ -113,7 +115,8 @@ void pm_set(unsigned mode) PWR_CR_REG &= ~(PM_STOP_CONFIG | PM_STANDBY_CONFIG); PWR_CR_REG |= PM_STANDBY_CONFIG; #if defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32WB) || \ - defined(CPU_FAM_STM32G4) || defined(CPU_FAM_STM32L5) + defined(CPU_FAM_STM32G4) || defined(CPU_FAM_STM32L5) || \ + defined(CPU_FAM_STM32WL) #if STM32L4_SRAM2_RETENTION PWR->CR3 |= PWR_CR3_RRS; #else diff --git a/cpu/stm32/stm32_info.mk b/cpu/stm32/stm32_info.mk index 67c4f4c497..21d06e6850 100644 --- a/cpu/stm32/stm32_info.mk +++ b/cpu/stm32/stm32_info.mk @@ -8,7 +8,7 @@ # - STM32_PINCOUNT: R (64) # - STM32_ROMSIZE: G (1024K) CPU_MODEL_UPPERCASE = $(call uppercase,$(CPU_MODEL)) -STM32_INFO := $(shell echo $(CPU_MODEL_UPPERCASE) | sed -E -e 's/^STM32(F|L|W|G|MP)([0-7]|B|L)([A-Z0-9])([0-9])(.)(.)?(_A)?/\1 \2 \2\3\4 \3 \4 \5 \6 \7/') +STM32_INFO := $(shell echo $(CPU_MODEL_UPPERCASE) | sed -E -e 's/^STM32(F|L|W|G|MP)([0-7]|B|L)([A-Z0-9])([0-9])(.)(.)?(_A)?/\1 \2 \2\3\4 \3 \4 \5 \6 \7/') STM32_TYPE = $(word 1, $(STM32_INFO)) STM32_FAMILY = $(word 2, $(STM32_INFO)) STM32_MODEL = $(word 3, $(STM32_INFO)) diff --git a/cpu/stm32/stmclk/Makefile b/cpu/stm32/stmclk/Makefile index 2cf77b8247..7c8e2b386a 100644 --- a/cpu/stm32/stmclk/Makefile +++ b/cpu/stm32/stmclk/Makefile @@ -11,7 +11,7 @@ else ifneq (,$(filter $(CPU_FAM),f0 f1 f3)) else ifneq (,$(filter $(CPU_FAM),l0 l1)) SRC += stmclk_l0l1.c else ifneq (,$(filter $(CPU_FAM),l4 wb wl)) - SRC += stmclk_l4wbwl.c + SRC += stmclk_l4wx.c else ifneq (,$(filter $(CPU_FAM),l5)) SRC += stmclk_l5.c else ifneq (,$(filter $(CPU_FAM),g0 g4)) diff --git a/cpu/stm32/stmclk/stmclk_l4wbwl.c b/cpu/stm32/stmclk/stmclk_l4wx.c similarity index 97% rename from cpu/stm32/stmclk/stmclk_l4wbwl.c rename to cpu/stm32/stmclk/stmclk_l4wx.c index fdfe38ef7d..e620edc624 100644 --- a/cpu/stm32/stmclk/stmclk_l4wbwl.c +++ b/cpu/stm32/stmclk/stmclk_l4wx.c @@ -330,18 +330,16 @@ /* Configure 48MHz clock source */ #define CLOCK_PLLQ ((CLOCK_PLL_SRC / CONFIG_CLOCK_PLL_M) * CONFIG_CLOCK_PLL_N) / CONFIG_CLOCK_PLL_Q -#if CLOCK_PLLQ == MHZ(48) +#if CLOCK_PLLQ == MHZ(48) && !defined(CPU_FAM_STM32WL) #define CLOCK48MHZ_USE_PLLQ 1 -#elif CONFIG_CLOCK_MSI == MHZ(48) +#elif CONFIG_CLOCK_MSI == MHZ(48) && !defined(CPU_FAM_STM32WL) #define CLOCK48MHZ_USE_MSI 1 #else #define CLOCK48MHZ_USE_PLLQ 0 #define CLOCK48MHZ_USE_MSI 0 #endif -#if defined(CPU_FAM_STM32WL) -#define CLOCK48MHZ_SELECT (0) -#elif IS_ACTIVE(CLOCK48MHZ_USE_PLLQ) +#if IS_ACTIVE(CLOCK48MHZ_USE_PLLQ) #define CLOCK48MHZ_SELECT (RCC_CCIPR_CLK48SEL_1) #elif IS_ACTIVE(CLOCK48MHZ_USE_MSI) #define CLOCK48MHZ_SELECT (RCC_CCIPR_CLK48SEL_1 | RCC_CCIPR_CLK48SEL_0) @@ -433,12 +431,20 @@ * @name Deduct the needed flash wait states from the core clock frequency * @{ */ -#if defined(CPU_FAM_STM32WB) || defined(CPU_FAM_STM32WL) +#if defined(CPU_FAM_STM32WL) +#if (CLOCK_AHB <= 16000000) /* VCORE range 2 */ +#define FLASH_WAITSTATES ((CLOCK_AHB - 1) / 6000000U) +#elif (CLOCK_AHB <= 48000000) /* VCORE range 1 */ +#define FLASH_WAITSTATES ((CLOCK_AHB - 1) / 18000000U) +#else +#define FLASH_WAITSTATES FLASH_ACR_LATENCY_2 +#endif /* CPU_FAM_STM32WL */ +#elif defined(CPU_FAM_STM32WB) #if (CLOCK_AHB <= 64000000) #define FLASH_WAITSTATES ((CLOCK_AHB - 1) / 18000000U) #else #define FLASH_WAITSTATES FLASH_ACR_LATENCY_3WS -#endif +#endif /* CPU_FAM_STM32WB */ #else #define FLASH_WAITSTATES ((CLOCK_AHB - 1) / 16000000U) #endif @@ -487,6 +493,11 @@ void stmclk_init_sysclk(void) - Use HSE as PLL input clock */ if (IS_ACTIVE(CLOCK_ENABLE_HSE)) { + + /* Use VDDTCXO regulator */ +#if defined(CPU_FAM_STM32WL) + RCC->CR |= (RCC_CR_HSEBYPPWR); +#endif RCC->CR |= (RCC_CR_HSEON); while (!(RCC->CR & RCC_CR_HSERDY)) {} }