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Merge pull request #10941 from keestux/update-samr30-vendor

cpu/samr30: update vendor files using ASF 3.35.1
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Alexandre Abadie 2019-10-02 13:35:06 +02:00 committed by GitHub
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26 changed files with 90 additions and 137 deletions

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@ -2,8 +2,7 @@
The include files in this directory tree are copied from Atmel
sources. Most of the sam0 files are from ASF (Atmel Software Foundation,
version 3.35.1). The SAMR30 files are from ASF 3.34.2. The SAML10 and
SAML11 files are from, so called, atpacks.
version 3.35.1). The SAML10 and SAML11 files are from, so called, atpacks.
## The sam0 files

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# CMSIS from Atmel Software Foundation (ASF)
The include files in the directory tree are copied from ASF. See
https://spaces.atmel.com/gf/project/asf/frs/?action=FrsReleaseBrowse&frs_package_id=4
(dd. 2017-04-13 ASF version 3.34.2 was used)
The directory tree was copied "as is" and its structure is as follows:
cmsis
└── samr30
├── include
│ ├── component
│ ├── instance
│ └── pio
└── source
├── gcc
└── iar
There is only one include file (per CPU variant) that should be included in
the source code. For SAMR30 that is cmsis/saml21/include/samr30.h. But
that will only work if the proper define is set. The define is named after
the variant, for example `__SAMR30G18A__`. This define must be set in the
`Makefile.include` of the board.
Be aware that if you want to make changes to any file in this tree that the
changes will be lost when a new ASF release is going to be used.
## Trailing White Space
Because of the whitespace check (dist/tools/whitespacecheck/check.sh) all
the trailing white space had to be removed. Please take this into account
when comparing to the original ASF distribution.
find include/ -name '*.h' -exec sed -i 's/\s*$//' '{}' +
find include_b/ -name '*.h' -exec sed -i 's/\s*$//' '{}' +
## LITTLE_ENDIAN
These include files define `LITTLE_ENDIAN`. But we think this is wrong. It
seems more logical to let the compiler decide in which mode the ARM code is
to be translated. In include/machine/endian.h there is already a define of
`LITTLE_ENDIAN` (and `BIG_ENDIAN`) for a different purpose.
So, we decided to remove the define from the ASF CMSIS files. The command
for it (running from this directory) is:
find include/ -name '*.h' -exec sed -i '/^#define\s\s*LITTLE_ENDIAN/d' '{}' +
find include_b/ -name '*.h' -exec sed -i '/^#define\s\s*LITTLE_ENDIAN/d' '{}' +

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@ -3,7 +3,7 @@
*
* \brief Header file for SAMR30E18A
*
* Copyright (c) 2016 Atmel Corporation. All rights reserved.
* Copyright (c) 2017 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
@ -72,7 +72,7 @@ typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatil
#endif
typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */
typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */
typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */
@ -217,6 +217,7 @@ void PTC_Handler ( void );
* \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
*/
#define LITTLE_ENDIAN 1
#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
#define __MPU_PRESENT 0 /*!< MPU present or not */
#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */

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@ -3,7 +3,7 @@
*
* \brief Header file for SAMR30G18A
*
* Copyright (c) 2016 Atmel Corporation. All rights reserved.
* Copyright (c) 2017 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
@ -72,7 +72,7 @@ typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatil
#endif
typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */
typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */
typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */
@ -217,6 +217,7 @@ void PTC_Handler ( void );
* \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
*/
#define LITTLE_ENDIAN 1
#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
#define __MPU_PRESENT 0 /*!< MPU present or not */
#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */