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Merge pull request #6615 from aabadie/nucleo_f302

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boards/nucleo-f302: initial support
This commit is contained in:
Francisco Acosta 2017-03-16 17:58:14 +01:00 committed by GitHub
commit f839e73b1a
21 changed files with 12716 additions and 28 deletions
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3
boards/nucleo-f302/Makefile Executable file
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MODULE = board
include $(RIOTBASE)/Makefile.base

1
boards/nucleo-f302/Makefile.dep Normal file
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include $(RIOTBOARD)/nucleo-common/Makefile.dep

14
boards/nucleo-f302/Makefile.features Executable file
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# Put defined MCU peripherals here (in alphabetical order)
FEATURES_PROVIDED += periph_cpuid
FEATURES_PROVIDED += periph_gpio
FEATURES_PROVIDED += periph_i2c
FEATURES_PROVIDED += periph_pwm
FEATURES_PROVIDED += periph_spi
FEATURES_PROVIDED += periph_timer
FEATURES_PROVIDED += periph_uart
# load the common Makefile.features for Nucleo boards
include $(RIOTBOARD)/nucleo-common/Makefile.features
# The board MPU family (used for grouping by the CI system)
FEATURES_MCU_GROUP = cortex_m4_2

6
boards/nucleo-f302/Makefile.include Executable file
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# the cpu to build for
export CPU = stm32f3
export CPU_MODEL = stm32f302r8
# load the common Makefile.include for Nucleo boards
include $(RIOTBOARD)/nucleo-common/Makefile.include

31
boards/nucleo-f302/board.c Executable file
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/*
* Copyright (C) 2015 Freie Universität Berlin
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @ingroup boards_nucleo-f303
* @{
*
* @file
* @brief Board specific implementations for the nucleo-f303 board
*
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
*
* @}
*/
#include "board.h"
#include "periph/gpio.h"
void board_init(void)
{
/* initialize the CPU */
cpu_init();
/* initialize the boards LEDs */
gpio_init(LED0_PIN, GPIO_OUT);
}

1
boards/nucleo-f302/dist/openocd.cfg vendored Executable file
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source [find board/st_nucleo_f3.cfg]

62
boards/nucleo-f302/include/board.h Executable file
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/*
* Copyright (C) 2017 Inria
* Copyright (C) 2015 Freie Universität Berlin
* Copyright (C) 2015 Hamburg University of Applied Sciences
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @defgroup boards_nucleo-f302 Nucleo-F302
* @ingroup boards
* @brief Board specific files for the nucleo-f302 board
* @{
*
* @file
* @brief Board specific definitions for the nucleo-f302 board
*
* @author Alexandre Abadie <alexandre.abadie@inria.fr>
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
* @author Katja Kirstein <katja.kirstein@haw-hamburg.de>
*/
#ifndef BOARD_H
#define BOARD_H
#include "cpu.h"
#include "periph_conf.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief LED pin definitions and handlers
* @{
*/
#define LED0_PIN GPIO_PIN(PORT_B, 13)
#define LED0_MASK (1 << 13)
#define LED0_ON (GPIOB->BSRR = LED0_MASK)
#define LED0_OFF (GPIOB->BSRR = (LED0_MASK << 16))
#define LED0_TOGGLE (GPIOB->ODR ^= LED0_MASK)
/** @} */
/**
* @brief User button
*/
#define BTN_B1_PIN GPIO_PIN(PORT_C, 13)
/**
* @brief Initialize board specific hardware, including clock, LEDs and std-IO
*/
void board_init(void);
#ifdef __cplusplus
}
#endif
#endif /* BOARD_H */
/** @} */

240
boards/nucleo-f302/include/periph_conf.h Executable file
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/*
* Copyright (C) 2017 Inria
* Copyright (C) 2015 Freie Universität Berlin
* Copyright (C) 2015 Hamburg University of Applied Sciences
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @ingroup boards_nucleo-f302 Nucleo-F302
* @{
*
* @file
* @brief Peripheral MCU configuration for the nucleo-f302 board
*
* @author Alexandre Abadie <alexandre.abadie@inria.fr>
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
* @author Katja Kirstein <katja.kirstein@haw-hamburg.de>
*/
#ifndef PERIPH_CONF_H
#define PERIPH_CONF_H
#include "periph_cpu.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @name Clock system configuration
* @{
*/
#define CLOCK_HSE (8000000U) /* external oscillator */
#define CLOCK_CORECLOCK (72000000U) /* desired core clock frequency */
/* the actual PLL values are automatically generated */
#define CLOCK_PLL_MUL (CLOCK_CORECLOCK / CLOCK_HSE)
#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1
#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2
#define CLOCK_FLASH_LATENCY FLASH_ACR_LATENCY_1
/* bus clocks for simplified peripheral initialization, UPDATE MANUALLY! */
#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
#define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
#define CLOCK_APB1 (CLOCK_CORECLOCK / 2)
/** @} */
/**
* @name ADC configuration
* @{
*/
#define ADC_NUMOF (0)
/** @} */
/**
* @name DAC configuration
* @{
*/
#define DAC_NUMOF (0)
/** @} */
/**
* @name Timer configuration
* @{
*/
static const timer_conf_t timer_config[] = {
{
.dev = TIM2,
.max = 0xffffffff,
.rcc_mask = RCC_APB1ENR_TIM2EN,
.bus = APB1,
.irqn = TIM2_IRQn
}
};
#define TIMER_0_ISR isr_tim2
#define TIMER_NUMOF (sizeof(timer_config) / sizeof(timer_config[0]))
/** @} */
/**
* @name UART configuration
* @{
*/
static const uart_conf_t uart_config[] = {
{
.dev = USART2,
.rcc_mask = RCC_APB1ENR_USART2EN,
.rx_pin = GPIO_PIN(PORT_A, 3),
.tx_pin = GPIO_PIN(PORT_A, 2),
.rx_af = GPIO_AF7,
.tx_af = GPIO_AF7,
.bus = APB1,
.irqn = USART2_IRQn
},
{
.dev = USART1,
.rcc_mask = RCC_APB2ENR_USART1EN,
.rx_pin = GPIO_PIN(PORT_A, 10),
.tx_pin = GPIO_PIN(PORT_A, 9),
.rx_af = GPIO_AF7,
.tx_af = GPIO_AF7,
.bus = APB2,
.irqn = USART1_IRQn
},
{
.dev = USART3,
.rcc_mask = RCC_APB1ENR_USART3EN,
.rx_pin = GPIO_PIN(PORT_C, 11),
.tx_pin = GPIO_PIN(PORT_C, 10),
.rx_af = GPIO_AF7,
.tx_af = GPIO_AF7,
.bus = APB1,
.irqn = USART3_IRQn
}
};
#define UART_0_ISR (isr_usart2)
#define UART_1_ISR (isr_usart1)
#define UART_2_ISR (isr_usart3)
#define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0]))
/** @} */
/**
* @name PWM configuration
* @{
*/
static const pwm_conf_t pwm_config[] = {
{
.dev = TIM16,
.rcc_mask = RCC_APB2ENR_TIM16EN,
.chan = { { .pin = GPIO_PIN(PORT_B, 4) /* D5 */, .cc_chan = 0 },
{ .pin = GPIO_UNDEF, .cc_chan = 0 },
{ .pin = GPIO_UNDEF, .cc_chan = 0 },
{ .pin = GPIO_UNDEF, .cc_chan = 0 } },
.af = GPIO_AF1,
.bus = APB2
}
};
#define PWM_NUMOF (sizeof(pwm_config) / sizeof(pwm_config[0]))
/** @} */
/**
* @name SPI configuration
*
* @note The spi_divtable is auto-generated from
* `cpu/stm32_common/dist/spi_divtable/spi_divtable.c`
* @{
*/
static const uint8_t spi_divtable[2][5] = {
{ /* for APB1 @ 36000000Hz */
7, /* -> 140625Hz */
6, /* -> 281250Hz */
4, /* -> 1125000Hz */
2, /* -> 4500000Hz */
1 /* -> 9000000Hz */
},
{ /* for APB2 @ 72000000Hz */
7, /* -> 281250Hz */
7, /* -> 281250Hz */
5, /* -> 1125000Hz */
3, /* -> 4500000Hz */
2 /* -> 9000000Hz */
}
};
static const spi_conf_t spi_config[] = {
{
.dev = SPI2,
.mosi_pin = GPIO_PIN(PORT_B, 15),
.miso_pin = GPIO_PIN(PORT_B, 14),
.sclk_pin = GPIO_PIN(PORT_B, 13),
.cs_pin = GPIO_PIN(PORT_B, 12),
.af = GPIO_AF5,
.rccmask = RCC_APB1ENR_SPI2EN,
.apbbus = APB1
}
};
#define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
/** @} */
/**
* @name I2C configuration
* @{
*/
#define I2C_NUMOF (2U)
#define I2C_0_EN 1
#define I2C_1_EN 1
#define I2C_IRQ_PRIO 1
#define I2C_APBCLK (36000000U)
/* I2C 0 device configuration */
#define I2C_0_DEV I2C1
#define I2C_0_CLKEN() (periph_clk_en(APB1, RCC_APB1ENR_I2C1EN))
#define I2C_0_CLKDIS() (periph_clk_dis(APB1, RCC_APB1ENR_I2C1EN))
#define I2C_0_EVT_IRQ I2C1_EV_IRQn
#define I2C_0_EVT_ISR isr_i2c1_ev
#define I2C_0_ERR_IRQ I2C1_ER_IRQn
#define I2C_0_ERR_ISR isr_i2c1_er
/* I2C 0 pin configuration */
#define I2C_0_SCL_PORT GPIOB
#define I2C_0_SCL_PIN 8
#define I2C_0_SCL_AF 4
#define I2C_0_SCL_CLKEN() (periph_clk_en(AHB, RCC_AHBENR_GPIOBEN))
#define I2C_0_SDA_PORT GPIOB
#define I2C_0_SDA_PIN 9
#define I2C_0_SDA_AF 4
#define I2C_0_SDA_CLKEN() (periph_clk_en(AHB, RCC_AHBENR_GPIOBEN))
/* I2C 1 device configuration */
#define I2C_1_DEV I2C3
#define I2C_1_CLKEN() (periph_clk_en(APB1, RCC_APB1ENR_I2C3EN))
#define I2C_1_CLKDIS() (periph_clk_dis(APB1, RCC_APB1ENR_I2C3EN))
#define I2C_1_EVT_IRQ I2C3_EV_IRQn
#define I2C_1_EVT_ISR isr_i2c3_ev
#define I2C_1_ERR_IRQ I2C3_ER_IRQn
#define I2C_1_ERR_ISR isr_i2c3_er
/* I2C 1 pin configuration */
#define I2C_1_SCL_PORT GPIOA
#define I2C_1_SCL_PIN 8
#define I2C_1_SCL_AF 3
#define I2C_1_SCL_CLKEN() (periph_clk_en(AHB, RCC_AHBENR_GPIOAEN))
#define I2C_1_SDA_PORT GPIOB
#define I2C_1_SDA_PIN 5
#define I2C_1_SDA_AF 8
#define I2C_1_SDA_CLKEN() (periph_clk_en(AHB, RCC_AHBENR_GPIOBEN))
/** @} */
#ifdef __cplusplus
}
#endif
#endif /* PERIPH_CONF_H */

3
cpu/stm32f3/include/cpu_conf.h
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@ -36,6 +36,9 @@
#ifdef CPU_MODEL_STM32F303K8
#include "vendor/stm32f303x8.h"
#endif
#ifdef CPU_MODEL_STM32F302R8
#include "vendor/stm32f302x8.h"
#endif
#ifdef __cplusplus
extern "C" {
#endif

12296
cpu/stm32f3/include/vendor/stm32f302x8.h vendored Normal file
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30
cpu/stm32f3/ldscripts/stm32f302r8.ld Normal file
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/*
* Copyright (C) 2017 Inria
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @addtogroup cpu_stm32f3
* @{
*
* @file
* @brief Memory definitions for the STM32F302R8
*
* @author Alexandre Abadie <alexandre.abadie@inria.fr>
*
* @}
*/
MEMORY
{
rom (rx) : ORIGIN = 0x08000000, LENGTH = 64K
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 16K
cpuid (r) : ORIGIN = 0x1ffff7ac, LENGTH = 12
}
_cpuid_address = ORIGIN(cpuid);
INCLUDE cortexm_base.ld

6
examples/dtls-echo/Makefile
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@ -15,9 +15,9 @@ BOARD_BLACKLIST := arduino-duemilanove arduino-mega2560 arduino-uno chronos \
BOARD_INSUFFICIENT_MEMORY := airfy-beacon calliope-mini cc2650stk maple-mini \
microbit nrf51dongle nrf6310 nucleo32-f031 \
nucleo32-f042 nucleo32-f303 nucleo-f030 nucleo-f070 \
nucleo-f072 nucleo-f103 nucleo-f334 nucleo-l053 \
nucleo-l073 nucleo32-l031 opencm904 pca10000 pca10005 \
nucleo32-f042 nucleo32-f303 nucleo32-l031 nucleo-f030 \
nucleo-f070 nucleo-f072 nucleo-f103 nucleo-f302 nucleo-f334 \
nucleo-l053 nucleo-l073 opencm904 pca10000 pca10005 \
spark-core stm32f0discovery weio yunjia-nrf51822
# Include packages that pull up and auto-init the link layer.

5
examples/emcute/Makefile
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@ -10,8 +10,9 @@ RIOTBASE ?= $(CURDIR)/../..
BOARD_INSUFFICIENT_MEMORY := arduino-duemilanove arduino-mega2560 arduino-uno \
chronos msb-430 msb-430h nucleo32-f031 nucleo32-f042 \
nucleo32-f303 nucleo32-l031 nucleo-f030 nucleo-f070 \
nucleo-f072 nucleo-f334 nucleo-l053 stm32f0discovery \
telosb waspmote-pro weio wsn430-v1_3b wsn430-v1_4 z1
nucleo-f072 nucleo-f302 nucleo-f334 nucleo-l053 \
stm32f0discovery telosb waspmote-pro weio wsn430-v1_3b \
wsn430-v1_4 z1
# Include packages that pull up and auto-init the link layer.
# NOTE: 6LoWPAN will be included if IEEE802.15.4 devices are present

6
examples/gnrc_border_router/Makefile
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@ -10,9 +10,9 @@ RIOTBASE ?= $(CURDIR)/../..
BOARD_INSUFFICIENT_MEMORY := airfy-beacon calliope-mini cc2650stk maple-mini \
microbit msb-430 msb-430h nrf51dongle nrf6310 \
nucleo32-f031 nucleo32-f042 nucleo32-f303 nucleo32-l031 \
nucleo-f030 nucleo-f070 nucleo-f072 nucleo-f103 nucleo-f334 \
nucleo-l053 nucleo-l073 opencm904 pca10000 pca10005 \
spark-core stm32f0discovery telosb weio wsn430-v1_3b \
nucleo-f030 nucleo-f070 nucleo-f072 nucleo-f103 nucleo-f302 \
nucleo-f334 nucleo-l053 nucleo-l073 opencm904 pca10000 \
pca10005 spark-core stm32f0discovery telosb weio wsn430-v1_3b \
wsn430-v1_4 yunjia-nrf51822 z1
BOARD_BLACKLIST += mips-malta # No UART available.

6
examples/gnrc_networking/Makefile
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@ -9,9 +9,9 @@ RIOTBASE ?= $(CURDIR)/../..
BOARD_INSUFFICIENT_MEMORY := calliope-mini chronos microbit msb-430 msb-430h \
nucleo32-f031 nucleo32-f042 nucleo32-f303 nucleo32-l031 \
nucleo-f030 nucleo-f070 nucleo-f072 nucleo-f103 nucleo-f334 \
nucleo-l053 spark-core stm32f0discovery telosb weio \
wsn430-v1_3b wsn430-v1_4 z1
nucleo-f030 nucleo-f070 nucleo-f072 nucleo-f103 nucleo-f302 \
nucleo-f334 nucleo-l053 spark-core stm32f0discovery telosb \
weio wsn430-v1_3b wsn430-v1_4 z1
# Include packages that pull up and auto-init the link layer.
# NOTE: 6LoWPAN will be included if IEEE802.15.4 devices are present

6
examples/gnrc_tftp/Makefile
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@ -10,9 +10,9 @@ RIOTBASE ?= $(CURDIR)/../..
BOARD_INSUFFICIENT_MEMORY := airfy-beacon calliope-mini chronos microbit msb-430 \
msb-430h nrf51dongle nrf6310 nucleo32-f031 \
nucleo32-f042 nucleo32-f303 nucleo32-l031 nucleo-f030 \
nucleo-f070 nucleo-f072 nucleo-f103 nucleo-f334 nucleo-l053 \
pca10000 pca10005 spark-core stm32f0discovery telosb \
weio wsn430-v1_3b wsn430-v1_4 yunjia-nrf51822 z1
nucleo-f070 nucleo-f072 nucleo-f103 nucleo-f302 nucleo-f334 \
nucleo-l053 pca10000 pca10005 spark-core stm32f0discovery \
telosb weio wsn430-v1_3b wsn430-v1_4 yunjia-nrf51822 z1
# Include packages that pull up and auto-init the link layer.
# NOTE: 6LoWPAN will be included if IEEE802.15.4 devices are present

6
tests/gnrc_tcp_client/Makefile
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@ -14,9 +14,9 @@ BOARD_INSUFFICIENT_MEMORY := airfy-beacon arduino-duemilanove arduino-mega2560 \
arduino-uno calliope-mini chronos microbit msb-430 \
msb-430h nrf51dongle nrf6310 nucleo32-f031 \
nucleo32-f042 nucleo32-f303 nucleo32-l031 nucleo-f030 \
nucleo-f070 nucleo-f072 nucleo-f334 nucleo-l053 pca10000 \
pca10005 sb-430 sb-430h stm32f0discovery telosb weio \
wsn430-v1_3b wsn430-v1_4 yunjia-nrf51822 z1
nucleo-f070 nucleo-f072 nucleo-f302 nucleo-f334 nucleo-l053 \
pca10000 pca10005 sb-430 sb-430h stm32f0discovery telosb \
weio wsn430-v1_3b wsn430-v1_4 yunjia-nrf51822 z1
# This has to be the absolute path to the RIOT base directory:
RIOTBASE ?= $(CURDIR)/../..

6
tests/gnrc_tcp_server/Makefile
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@ -12,9 +12,9 @@ BOARD_INSUFFICIENT_MEMORY := airfy-beacon arduino-duemilanove arduino-mega2560 \
arduino-uno calliope-mini chronos microbit msb-430 \
msb-430h nrf51dongle nrf6310 nucleo32-f031 \
nucleo32-f042 nucleo32-f303 nucleo32-l031 nucleo-f030 \
nucleo-f070 nucleo-f072 nucleo-f334 nucleo-l053 pca10000 \
pca10005 sb-430 sb-430h stm32f0discovery telosb weio \
wsn430-v1_3b wsn430-v1_4 yunjia-nrf51822 z1
nucleo-f070 nucleo-f072 nucleo-f302 nucleo-f334 nucleo-l053 \
pca10000 pca10005 sb-430 sb-430h stm32f0discovery telosb \
weio wsn430-v1_3b wsn430-v1_4 yunjia-nrf51822 z1
# This has to be the absolute path to the RIOT base directory:
RIOTBASE ?= $(CURDIR)/../..

6
tests/lwip/Makefile
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@ -8,9 +8,9 @@ RIOTBASE ?= $(CURDIR)/../..
BOARD_BLACKLIST := arduino-mega2560 msb-430h telosb waspmote-pro z1 arduino-uno \
arduino-duemilanove msb-430 wsn430-v1_4 wsn430-v1_3b
BOARD_INSUFFICIENT_MEMORY := airfy-beacon arduino-mega2560 msb-430h nrf6310 \
nucleo32-f031 nucleo-f030 nucleo-f072 nucleo-f334 \
nucleo-l053 pca10005 stm32f0discovery telosb weio \
yunjia-nrf51822 z1
nucleo32-f031 nucleo-f030 nucleo-f072 nucleo-f302 \
nucleo-f334 nucleo-l053 pca10005 stm32f0discovery \
telosb weio yunjia-nrf51822 z1
# including lwip_ipv6_mld would currently break this test on at86rf2xx radios
USEMODULE += lwip lwip_ipv6_autoconfig lwip_conn_ip lwip_netdev

4
tests/thread_cooperation/Makefile
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@ -5,8 +5,8 @@ BOARD_INSUFFICIENT_MEMORY := airfy-beacon calliope-mini cc2650stk chronos maple-
mbed_lpc1768 microbit msb-430 msb-430h nrf51dongle \
nrf6310 nucleo32-f031 nucleo32-f042 nucleo32-f303 \
nucleo32-l031 nucleo-f030 nucleo-f070 nucleo-f072 \
nucleo-f103 nucleo-f334 nucleo-l053 nucleo-l073 opencm904 \
pca10000 pca10005 spark-core stm32f0discovery weio \
nucleo-f103 nucleo-f302 nucleo-f334 nucleo-l053 nucleo-l073 \
opencm904 pca10000 pca10005 spark-core stm32f0discovery weio \
yunjia-nrf51822
DISABLE_MODULE += auto_init

6
tests/unittests/Makefile
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@ -6,8 +6,8 @@ BOARD_INSUFFICIENT_MEMORY := airfy-beacon arduino-duemilanove arduino-mega2560 \
chronos ek-lm4f120xl limifrog-v1 maple-mini microbit \
msb-430 msb-430h nrf51dongle nrf6310 nucleo32-f031 \
nucleo32-f042 nucleo32-f303 nucleo32-l031 nucleo-f030 \
nucleo-f070 nucleo-f072 nucleo-f091 nucleo-f103 nucleo-f334 \
nucleo-f410 nucleo-l053 nucleo-l073 opencm904 \
nucleo-f070 nucleo-f072 nucleo-f091 nucleo-f103 nucleo-f302 \
nucleo-f334 nucleo-f410 nucleo-l053 nucleo-l073 opencm904 \
pba-d-01-kw2x pca10000 pca10005 remote-pa remote-reva \
remote-revb saml21-xpro samr21-xpro seeeduino_arch-pro \
slwstk6220a sodaq-autonomo spark-core stm32f0discovery \
@ -28,7 +28,7 @@ DISABLE_TEST_FOR_ARM7 := tests-relic
ARM_CORTEX_M_BOARDS := airfy-beacon arduino-due arduino-zero cc2538dk ek-lm4f120xl \
f4vi1 fox frdm-k64f iotlab-m3 limifrog-v1 mbed_lpc1768 msbiot \
mulle nrf51dongle nrf6310 nucleo32-f031 nucleo32-f303 nucleo32-l031 \
nucleo-f030 nucleo-f070 nucleo-f091 nucleo-f303 nucleo-f334 \
nucleo-f030 nucleo-f070 nucleo-f091 nucleo-f302 nucleo-f303 nucleo-f334 \
nucleo-f401 nucleo-f410 nucleo-f411 nucleo-l053 nucleo-l073 \
nucleo-l1 opencm904 openmote-cc2538 pba-d-01-kw2x pca10000 \
pca10005 remote saml21-xpro samr21-xpro slwstk6220a sodaq-autonomo \