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cpu/nrf51: use nrfxx_peripherals.h vendor header
Using the nrf51xx_peripherals.h vendor header unifies the nrf51 code tree with the nrf52 implementation. It is needed to prevent build errors with the optional nrfx package.
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@ -24,6 +24,7 @@
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#include "cpu_conf_common.h"
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#include "vendor/nrf51.h"
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#include "vendor/nrf51_bitfields.h"
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#include "vendor/nrf51822_peripherals.h"
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#ifdef __cplusplus
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extern "C" {
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@ -57,11 +58,6 @@ extern "C" {
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#define FLASHPAGE_WRITE_BLOCK_ALIGNMENT (4U)
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/** @} */
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/**
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* @brief nRF51 only has one GPIO block
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*/
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#define GPIO_COUNT (1U)
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/**
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* @brief Due to RAM restrictions, we need to limit the default GNRC packet
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* buffer size on these CPUs
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171
cpu/nrf51/include/vendor/nrf51822_peripherals.h
vendored
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171
cpu/nrf51/include/vendor/nrf51822_peripherals.h
vendored
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/*
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Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved.
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SPDX-License-Identifier: BSD-3-Clause
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice, this
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list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in the
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documentation and/or other materials provided with the distribution.
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3. Neither the name of Nordic Semiconductor ASA nor the names of its
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contributors may be used to endorse or promote products derived from this
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software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE
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ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
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LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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POSSIBILITY OF SUCH DAMAGE.
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*/
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/* This file is deprecated */
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#ifndef _NRF51822_PERIPHERALS_H
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#define _NRF51822_PERIPHERALS_H
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/* Clock Peripheral */
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#define CLOCK_PRESENT
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#define CLOCK_COUNT 1
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/* Power Peripheral */
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#define POWER_PRESENT
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#define POWER_COUNT 1
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#define POWER_FEATURE_RAMON_REGISTERS_PRESENT
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/* Non-Volatile Memory Controller */
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#define NVMC_PRESENT
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#define NVMC_COUNT 1
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/* Software Interrupts */
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#define SWI_PRESENT
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#define SWI_COUNT 6
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/* GPIO */
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#define GPIO_PRESENT
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#define GPIO_COUNT 1
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#define P0_PIN_NUM 32
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#define P0_FEATURE_PINS_PRESENT 0xFFFFFFFFUL
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/* MPU and BPROT */
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#define BPROT_PRESENT
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#define BPROT_REGIONS_SIZE 4096
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#define BPROT_REGIONS_NUM 64
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/* Radio */
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#define RADIO_PRESENT
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#define RADIO_COUNT 1
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#define RADIO_TXPOWER_TXPOWER_Max RADIO_TXPOWER_TXPOWER_Pos4dBm
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/* Accelerated Address Resolver */
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#define AAR_PRESENT
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#define AAR_COUNT 1
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#define AAR_MAX_IRK_NUM 8
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/* AES Electronic CodeBook mode encryption */
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#define ECB_PRESENT
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#define ECB_COUNT 1
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/* AES CCM mode encryption */
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#define CCM_PRESENT
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#define CCM_COUNT 1
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/* Peripheral to Peripheral Interconnect */
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#define PPI_PRESENT
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#define PPI_COUNT 1
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#define PPI_CH_NUM 16
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#define PPI_FIXED_CH_NUM 12
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#define PPI_GROUP_NUM 4
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/* Timer/Counter */
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#define TIMER_PRESENT
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#define TIMER_COUNT 3
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#define TIMER0_MAX_SIZE 32
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#define TIMER1_MAX_SIZE 16
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#define TIMER2_MAX_SIZE 16
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#define TIMER0_CC_NUM 4
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#define TIMER1_CC_NUM 4
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#define TIMER2_CC_NUM 4
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/* Real Time Counter */
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#define RTC_PRESENT
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#define RTC_COUNT 2
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#define RTC0_CC_NUM 3
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#define RTC1_CC_NUM 4
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/* RNG */
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#define RNG_PRESENT
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#define RNG_COUNT 1
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/* Watchdog Timer */
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#define WDT_PRESENT
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#define WDT_COUNT 1
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/* Temperature Sensor */
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#define TEMP_PRESENT
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#define TEMP_COUNT 1
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/* Serial Peripheral Interface Master */
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#define SPI_PRESENT
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#define SPI_COUNT 2
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/* Serial Peripheral Interface Slave with DMA */
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#define SPIS_PRESENT
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#define SPIS_COUNT 1
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#define SPIS1_EASYDMA_MAXCNT_SIZE 8
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/* Two Wire Interface Master */
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#define TWI_PRESENT
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#define TWI_COUNT 2
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/* Universal Asynchronous Receiver-Transmitter */
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#define UART_PRESENT
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#define UART_COUNT 1
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/* Quadrature Decoder */
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#define QDEC_PRESENT
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#define QDEC_COUNT 1
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/* Analog to Digital Converter */
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#define ADC_PRESENT
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#define ADC_COUNT 1
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/* GPIO Tasks and Events */
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#define GPIOTE_PRESENT
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#define GPIOTE_COUNT 1
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#define GPIOTE_CH_NUM 4
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/* Low Power Comparator */
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#define LPCOMP_PRESENT
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#define LPCOMP_COUNT 1
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#define LPCOMP_REFSEL_RESOLUTION 8
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#endif // _NRF51822_PERIPHERALS_H
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