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boards/udoo: removed system_sam3xa.c file
This commit is contained in:
Hauke Petersen
parent
dd129d0dde
commit
f6b65180bd
@ -1,213 +0,0 @@
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/*! \file *********************************************************************
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*
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* \brief Provides the low-level initialization functions that called
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* on chip startup.
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*
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* Copyright (c) 2012, Atmel Corporation
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*
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following condition is met:
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*
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* - Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the disclaimer below.
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*
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* Atmel's name may not be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
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* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
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* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* \par Purpose
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*
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* This file provides basic support for Cortex-M processor based
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* microcontrollers.
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*
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* \author Atmel Corporation: http://www.atmel.com \n
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* Support and FAQ: http://support.atmel.no/
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*
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******************************************************************************/
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#include "sam3x8e.h"
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/* @cond 0 */
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/**INDENT-OFF**/
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**INDENT-ON**/
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/* @endcond */
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/* Clock settings (84MHz) */
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#define SYS_BOARD_OSCOUNT (CKGR_MOR_MOSCXTST(0x8))
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#define SYS_BOARD_PLLAR (CKGR_PLLAR_ONE \
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| CKGR_PLLAR_MULA(0xdUL) \
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| CKGR_PLLAR_PLLACOUNT(0x3fUL) \
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| CKGR_PLLAR_DIVA(0x1UL))
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#define SYS_BOARD_MCKR (PMC_MCKR_PRES_CLK_2 | PMC_MCKR_CSS_PLLA_CLK)
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/* Clock Definitions */
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#define SYS_UTMIPLL (480000000UL) /* UTMI PLL frequency */
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#define SYS_CKGR_MOR_KEY_VALUE CKGR_MOR_KEY(0x37) /* Key to unlock MOR register */
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/* FIXME: should be generated by sock */
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uint32_t SystemCoreClock = CHIP_FREQ_MAINCK_RC_4MHZ;
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/**
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* \brief Setup the microcontroller system.
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* Initialize the System and update the SystemFrequency variable.
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*/
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void SystemInit(void)
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{
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/* Set FWS according to SYS_BOARD_MCKR configuration */
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EFC0->EEFC_FMR = EEFC_FMR_FWS(4);
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EFC1->EEFC_FMR = EEFC_FMR_FWS(4);
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/* Initialize main oscillator */
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if (!(PMC->CKGR_MOR & CKGR_MOR_MOSCSEL)) {
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PMC->CKGR_MOR = SYS_CKGR_MOR_KEY_VALUE | SYS_BOARD_OSCOUNT |
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CKGR_MOR_MOSCRCEN | CKGR_MOR_MOSCXTEN;
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while (!(PMC->PMC_SR & PMC_SR_MOSCXTS)) {
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}
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}
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/* Switch to 3-20MHz Xtal oscillator */
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PMC->CKGR_MOR = SYS_CKGR_MOR_KEY_VALUE | SYS_BOARD_OSCOUNT |
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CKGR_MOR_MOSCRCEN | CKGR_MOR_MOSCXTEN | CKGR_MOR_MOSCSEL;
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while (!(PMC->PMC_SR & PMC_SR_MOSCSELS)) {
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}
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PMC->PMC_MCKR = (PMC->PMC_MCKR & ~(uint32_t)PMC_MCKR_CSS_Msk) |
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PMC_MCKR_CSS_MAIN_CLK;
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while (!(PMC->PMC_SR & PMC_SR_MCKRDY)) {
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}
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/* Initialize PLLA */
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PMC->CKGR_PLLAR = SYS_BOARD_PLLAR;
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while (!(PMC->PMC_SR & PMC_SR_LOCKA)) {
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}
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/* Switch to main clock */
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PMC->PMC_MCKR = (SYS_BOARD_MCKR & ~PMC_MCKR_CSS_Msk) | PMC_MCKR_CSS_MAIN_CLK;
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while (!(PMC->PMC_SR & PMC_SR_MCKRDY)) {
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}
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/* Switch to PLLA */
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PMC->PMC_MCKR = SYS_BOARD_MCKR;
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while (!(PMC->PMC_SR & PMC_SR_MCKRDY)) {
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}
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SystemCoreClock = CHIP_FREQ_CPU_MAX;
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}
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void SystemCoreClockUpdate(void)
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{
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/* Determine clock frequency according to clock register values */
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switch (PMC->PMC_MCKR & PMC_MCKR_CSS_Msk) {
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case PMC_MCKR_CSS_SLOW_CLK: /* Slow clock */
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if (SUPC->SUPC_SR & SUPC_SR_OSCSEL) {
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SystemCoreClock = CHIP_FREQ_XTAL_32K;
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} else {
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SystemCoreClock = CHIP_FREQ_SLCK_RC;
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}
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break;
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case PMC_MCKR_CSS_MAIN_CLK: /* Main clock */
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if (PMC->CKGR_MOR & CKGR_MOR_MOSCSEL) {
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SystemCoreClock = CHIP_FREQ_XTAL_12M;
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} else {
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SystemCoreClock = CHIP_FREQ_MAINCK_RC_4MHZ;
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switch (PMC->CKGR_MOR & CKGR_MOR_MOSCRCF_Msk) {
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case CKGR_MOR_MOSCRCF_4_MHz:
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break;
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case CKGR_MOR_MOSCRCF_8_MHz:
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SystemCoreClock *= 2U;
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break;
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case CKGR_MOR_MOSCRCF_12_MHz:
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SystemCoreClock *= 3U;
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break;
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default:
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break;
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}
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}
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break;
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case PMC_MCKR_CSS_PLLA_CLK: /* PLLA clock */
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case PMC_MCKR_CSS_UPLL_CLK: /* UPLL clock */
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if (PMC->CKGR_MOR & CKGR_MOR_MOSCSEL) {
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SystemCoreClock = CHIP_FREQ_XTAL_12M;
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} else {
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SystemCoreClock = CHIP_FREQ_MAINCK_RC_4MHZ;
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switch (PMC->CKGR_MOR & CKGR_MOR_MOSCRCF_Msk) {
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case CKGR_MOR_MOSCRCF_4_MHz:
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break;
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case CKGR_MOR_MOSCRCF_8_MHz:
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SystemCoreClock *= 2U;
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break;
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case CKGR_MOR_MOSCRCF_12_MHz:
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SystemCoreClock *= 3U;
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break;
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default:
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break;
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}
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}
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if ((PMC->PMC_MCKR & PMC_MCKR_CSS_Msk) == PMC_MCKR_CSS_PLLA_CLK) {
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SystemCoreClock *= ((((PMC->CKGR_PLLAR) & CKGR_PLLAR_MULA_Msk) >>
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CKGR_PLLAR_MULA_Pos) + 1U);
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SystemCoreClock /= ((((PMC->CKGR_PLLAR) & CKGR_PLLAR_DIVA_Msk) >>
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CKGR_PLLAR_DIVA_Pos));
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} else {
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SystemCoreClock = SYS_UTMIPLL / 2U;
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}
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break;
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}
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if ((PMC->PMC_MCKR & PMC_MCKR_PRES_Msk) == PMC_MCKR_PRES_CLK_3) {
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SystemCoreClock /= 3U;
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} else {
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SystemCoreClock >>= ((PMC->PMC_MCKR & PMC_MCKR_PRES_Msk) >>
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PMC_MCKR_PRES_Pos);
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}
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}
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/**
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* Initialize flash.
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*/
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void system_init_flash(uint32_t dw_clk)
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{
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/* Set FWS for embedded Flash access according to operating frequency */
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if (dw_clk < CHIP_FREQ_FWS_0) {
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EFC0->EEFC_FMR = EEFC_FMR_FWS(0);
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EFC1->EEFC_FMR = EEFC_FMR_FWS(0);
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} else if (dw_clk < CHIP_FREQ_FWS_1) {
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EFC0->EEFC_FMR = EEFC_FMR_FWS(1);
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EFC1->EEFC_FMR = EEFC_FMR_FWS(1);
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} else if (dw_clk < CHIP_FREQ_FWS_2) {
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EFC0->EEFC_FMR = EEFC_FMR_FWS(2);
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EFC1->EEFC_FMR = EEFC_FMR_FWS(2);
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} else if (dw_clk < CHIP_FREQ_FWS_3) {
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EFC0->EEFC_FMR = EEFC_FMR_FWS(3);
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EFC1->EEFC_FMR = EEFC_FMR_FWS(3);
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} else {
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EFC0->EEFC_FMR = EEFC_FMR_FWS(4);
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EFC1->EEFC_FMR = EEFC_FMR_FWS(4);
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}
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}
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/* @cond 0 */
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/**INDENT-OFF**/
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#ifdef __cplusplus
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}
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#endif
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/**INDENT-ON**/
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/* @endcond */
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