From f58a021f6da2f7df4a2960bad0186fc50f58843d Mon Sep 17 00:00:00 2001 From: Akshai M Date: Wed, 7 Jul 2021 13:41:56 +0200 Subject: [PATCH] cpu/stm32wl : Add HW Debug pins --- cpu/stm32/cpu_init.c | 51 ++++++++++++++ cpu/stm32/include/periph/wl/periph_cpu.h | 89 ++++++++++++++++++++++++ cpu/stm32/kconfigs/wl/Kconfig | 9 +++ 3 files changed, 149 insertions(+) diff --git a/cpu/stm32/cpu_init.c b/cpu/stm32/cpu_init.c index b94613888a..0e625850b0 100644 --- a/cpu/stm32/cpu_init.c +++ b/cpu/stm32/cpu_init.c @@ -37,6 +37,7 @@ #include "stmclk.h" #include "periph_cpu.h" #include "periph/init.h" +#include "periph/gpio.h" #include "board.h" #if defined (CPU_FAM_STM32L4) || defined (CPU_FAM_STM32G4) || \ @@ -151,6 +152,52 @@ static void _gpio_init_ain(void) } #endif +/** + * @brief Initialize HW debug pins for Sub-GHz Radio + */ +void _wl55jc_init_subghz_debug_pins(void) +{ +#if IS_ACTIVE(CONFIG_STM32_WL55JC_SUBGHZ_DEBUG) + /* SUBGHZSPI Debug */ + gpio_init(CPU_STM32WL_SUBGHZSPI_DEBUG_MOSIOUT, GPIO_OUT); + gpio_init_af(CPU_STM32WL_SUBGHZSPI_DEBUG_MOSIOUT, + CPU_STM32WL_SUBGHZSPI_DEBUG_MOSIOUT_AF); + + gpio_init(CPU_STM32WL_SUBGHZSPI_DEBUG_MISOOUT, GPIO_OUT); + gpio_init_af(CPU_STM32WL_SUBGHZSPI_DEBUG_MISOOUT, + CPU_STM32WL_SUBGHZSPI_DEBUG_MISOOUT_AF); + + gpio_init(CPU_STM32WL_SUBGHZSPI_DEBUG_SCKOUT, GPIO_OUT); + gpio_init_af(CPU_STM32WL_SUBGHZSPI_DEBUG_SCKOUT, + CPU_STM32WL_SUBGHZSPI_DEBUG_SCKOUT_AF); + + gpio_init(CPU_STM32WL_SUBGHZSPI_DEBUG_NSSOUT, GPIO_OUT); + gpio_init_af(CPU_STM32WL_SUBGHZSPI_DEBUG_NSSOUT, + CPU_STM32WL_SUBGHZSPI_DEBUG_NSSOUT_AF); + + /* Sub-GHz Radio Debug */ + gpio_init(CPU_STM32WL_SUBGHZ_RF_BUSY, GPIO_OUT); + gpio_init_af(CPU_STM32WL_SUBGHZ_RF_BUSY, + CPU_STM32WL_SUBGHZ_RF_BUSY_AF); + + gpio_init(CPU_STM32WL_SUBGHZ_DEBUG_RF_NRESET, GPIO_OUT); + gpio_init_af(CPU_STM32WL_SUBGHZ_DEBUG_RF_NRESET, + CPU_STM32WL_SUBGHZ_DEBUG_RF_NRESET_AF); + + gpio_init(CPU_STM32WL_SUBGHZ_DEBUG_RF_SMPSRDY, GPIO_OUT); + gpio_init_af(CPU_STM32WL_SUBGHZ_DEBUG_RF_SMPSRDY, + CPU_STM32WL_SUBGHZ_DEBUG_RF_SMPSRDY_AF); + + gpio_init(CPU_STM32WL_SUBGHZ_DEBUG_RF_LDORDY, GPIO_OUT); + gpio_init_af(CPU_STM32WL_SUBGHZ_DEBUG_RF_LDORDY, + CPU_STM32WL_SUBGHZ_DEBUG_RF_LDORDY_AF); + + gpio_init(CPU_STM32WL_SUBGHZ_DEBUG_RF_HSE32RDY, GPIO_OUT); + gpio_init_af(CPU_STM32WL_SUBGHZ_DEBUG_RF_HSE32RDY, + CPU_STM32WL_SUBGHZ_DEBUG_RF_HSE32RDY_AF); +#endif +} + void cpu_init(void) { /* initialize the Cortex-M core */ @@ -184,4 +231,8 @@ void cpu_init(void) /* trigger static peripheral initialization */ periph_init(); + + if (IS_ACTIVE(CONFIG_STM32_WL55JC_SUBGHZ_DEBUG)) { + _wl55jc_init_subghz_debug_pins(); + } } diff --git a/cpu/stm32/include/periph/wl/periph_cpu.h b/cpu/stm32/include/periph/wl/periph_cpu.h index c3ae86de89..afb34a5527 100644 --- a/cpu/stm32/include/periph/wl/periph_cpu.h +++ b/cpu/stm32/include/periph/wl/periph_cpu.h @@ -34,6 +34,95 @@ extern "C" { #endif /* ndef DOXYGEN */ +/** + * @defgroup cpu_stm32_wl_debug STM32WL hardware debugging + * @ingroup cpu_stm32 + * @{ + */ +/** + * @defgroup cpu_stm32_wl_debug_subghz_spi STM32WL Sub-GHz SPI debug pins + * @ingroup cpu_stm32_wl_debug + * @{ + */ +#define CPU_STM32WL_SUBGHZSPI_DEBUG_MOSIOUT GPIO_PIN(PORT_A, 7) +#define CPU_STM32WL_SUBGHZSPI_DEBUG_MOSIOUT_AF GPIO_AF13 + +#define CPU_STM32WL_SUBGHZSPI_DEBUG_MISOOUT GPIO_PIN(PORT_A, 6) +#define CPU_STM32WL_SUBGHZSPI_DEBUG_MISOOUT_AF GPIO_AF13 + +#define CPU_STM32WL_SUBGHZSPI_DEBUG_SCKOUT GPIO_PIN(PORT_A, 5) +#define CPU_STM32WL_SUBGHZSPI_DEBUG_SCKOUT_AF GPIO_AF13 + +#define CPU_STM32WL_SUBGHZSPI_DEBUG_NSSOUT GPIO_PIN(PORT_A, 4) +#define CPU_STM32WL_SUBGHZSPI_DEBUG_NSSOUT_AF GPIO_AF13 +/** @} */ +/** @} */ + +/** + * @defgroup cpu_stm32_wl_debug_subghz_radio STM32WL Sub-GHz Radio debug pins + * @ingroup cpu_stm32_wl_debug + * @{ + */ +/*! + * RF BUSY debug pin definition + */ +#define CPU_STM32WL_SUBGHZ_RF_BUSY GPIO_PIN(PORT_A, 12) +/*! + * RF BUSY debug pin alternate function + */ +#define CPU_STM32WL_SUBGHZ_RF_BUSY_AF GPIO_AF6 + +/*! + * RF NRESET debug pin definition + */ +#define CPU_STM32WL_SUBGHZ_DEBUG_RF_NRESET GPIO_PIN(PORT_A, 11) +/*! + * RF NRESET debug pin alternate function + */ +#define CPU_STM32WL_SUBGHZ_DEBUG_RF_NRESET_AF GPIO_AF13 + +/*! + * RF SMPSRDY debug pin definition + */ +#define CPU_STM32WL_SUBGHZ_DEBUG_RF_SMPSRDY GPIO_PIN(PORT_B, 2) +/*! + * RF SMPSRDY debug pin alternate function + */ +#define CPU_STM32WL_SUBGHZ_DEBUG_RF_SMPSRDY_AF GPIO_AF13 + +/*! + * RF LDORDY debug pin definition + */ +#define CPU_STM32WL_SUBGHZ_DEBUG_RF_LDORDY GPIO_PIN(PORT_B, 4) +/*! + * RF LDORDY debug pin alternate function + */ +#define CPU_STM32WL_SUBGHZ_DEBUG_RF_LDORDY_AF GPIO_AF13 + +/*! + * RF HSE32RDY debug pin definition + */ +#define CPU_STM32WL_SUBGHZ_DEBUG_RF_HSE32RDY GPIO_PIN(PORT_A, 10) +/*! + * RF HSE32RDY debug pin alternate function + */ +#define CPU_STM32WL_SUBGHZ_DEBUG_RF_HSE32RDY_AF GPIO_AF13 +/** @} */ + +/** + * @defgroup cpu_stm32_wl_config STM32WL compile time configuration + * @ingroup cpu_stm32_wl_debug + * @ingroup config_cpu + * @{ + */ +/** + * @brief Set this to 1 to enable hardware debugging. + */ +#ifdef DOXYGEN +#define CONFIG_STM32_WL55JC_SUBGHZ_DEBUG +#endif +/** @} */ + #ifdef __cplusplus } #endif diff --git a/cpu/stm32/kconfigs/wl/Kconfig b/cpu/stm32/kconfigs/wl/Kconfig index 8729dbb112..fb9406bd45 100644 --- a/cpu/stm32/kconfigs/wl/Kconfig +++ b/cpu/stm32/kconfigs/wl/Kconfig @@ -1,4 +1,5 @@ # Copyright (c) 2021 Inria +# Copyright (c) 2021 Freie Universitaet Berlin # # This file is subject to the terms and conditions of the GNU Lesser # General Public License v2.1. See the file LICENSE in the top level @@ -22,3 +23,11 @@ config HAS_CPU_STM32WL bool help Indicates that the cpu being used belongs to the 'stm32wl' family. + +config STM32_WL55JC_SUBGHZ_DEBUG + bool "STM32WL->Enable Hardware Debugging" + help + Enable Hardware debug pins. This would affect onboard peripherals such as SPI + as the pins are multiplexed. For more information check Alternate Functions + column in Table 19 : STM32WL55/54xx pin definition in STM32WL55/54xx + datasheet.