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cpu/nrf5x: provide specific gpio_t definition

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Alexandre Abadie 2020-02-19 14:38:12 +01:00
parent 953e8c9c15
commit f568162f9b
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GPG Key ID: 1C919A403CAE1405
3 changed files with 20 additions and 12 deletions
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4
cpu/nrf51/include/periph_cpu.h
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@ -88,8 +88,8 @@ typedef enum {
*/ */
typedef struct { typedef struct {
NRF_TWI_Type *dev; /**< hardware device */ NRF_TWI_Type *dev; /**< hardware device */
uint8_t pin_scl; /**< SCL pin */ gpio_t pin_scl; /**< SCL pin */
uint8_t pin_sda; /**< SDA pin */ gpio_t pin_sda; /**< SDA pin */
uint8_t ppi; /**< PPI channel to use */ uint8_t ppi; /**< PPI channel to use */
i2c_speed_t speed; /**< bus speed */ i2c_speed_t speed; /**< bus speed */
} i2c_conf_t; } i2c_conf_t;

14
cpu/nrf52/include/periph_cpu.h
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@ -105,8 +105,8 @@ typedef enum {
*/ */
typedef struct { typedef struct {
NRF_TWIM_Type *dev; /**< TWIM hardware device */ NRF_TWIM_Type *dev; /**< TWIM hardware device */
uint8_t scl; /**< SCL pin */ gpio_t scl; /**< SCL pin */
uint8_t sda; /**< SDA pin */ gpio_t sda; /**< SDA pin */
i2c_speed_t speed; /**< Bus speed */ i2c_speed_t speed; /**< Bus speed */
} i2c_conf_t; } i2c_conf_t;
/** @} */ /** @} */
@ -158,7 +158,7 @@ typedef enum {
*/ */
typedef struct { typedef struct {
NRF_PWM_Type *dev; /**< PWM device descriptor */ NRF_PWM_Type *dev; /**< PWM device descriptor */
uint32_t pin[PWM_CHANNELS]; /**< PWM out pins */ gpio_t pin[PWM_CHANNELS]; /**< PWM out pins */
} pwm_conf_t; } pwm_conf_t;
#ifdef CPU_MODEL_NRF52840XXAA #ifdef CPU_MODEL_NRF52840XXAA
@ -167,10 +167,10 @@ typedef struct {
*/ */
typedef struct { typedef struct {
NRF_UARTE_Type *dev; /**< UART with EasyDMA device base register address */ NRF_UARTE_Type *dev; /**< UART with EasyDMA device base register address */
uint8_t rx_pin; /**< RX pin */ gpio_t rx_pin; /**< RX pin */
uint8_t tx_pin; /**< TX pin */ gpio_t tx_pin; /**< TX pin */
uint8_t rts_pin; /**< RTS pin - set to GPIO_UNDEF when not using HW flow control */ gpio_t rts_pin; /**< RTS pin - set to GPIO_UNDEF when not using HW flow control */
uint8_t cts_pin; /**< CTS pin - set to GPIO_UNDEF when not using HW flow control */ gpio_t cts_pin; /**< CTS pin - set to GPIO_UNDEF when not using HW flow control */
uint8_t irqn; /**< IRQ channel */ uint8_t irqn; /**< IRQ channel */
} uart_conf_t; } uart_conf_t;
#endif #endif

14
cpu/nrf5x_common/include/periph_cpu_common.h
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@ -84,6 +84,14 @@ extern "C" {
/** @} */ /** @} */
#ifndef DOXYGEN #ifndef DOXYGEN
/**
* @brief Overwrite the default gpio_t type definition
* @{
*/
#define HAVE_GPIO_T
typedef uint8_t gpio_t;
/** @} */
/** /**
* @brief Override GPIO modes * @brief Override GPIO modes
* *
@ -162,9 +170,9 @@ typedef enum {
*/ */
typedef struct { typedef struct {
NRF_SPI_Type *dev; /**< SPI device used */ NRF_SPI_Type *dev; /**< SPI device used */
uint8_t sclk; /**< CLK pin */ gpio_t sclk; /**< CLK pin */
uint8_t mosi; /**< MOSI pin */ gpio_t mosi; /**< MOSI pin */
uint8_t miso; /**< MISO pin */ gpio_t miso; /**< MISO pin */
} spi_conf_t; } spi_conf_t;
/** /**