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cpu/msp430/periph_uart: Fix uart_write() for USCI peripheral

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In TX-only mode the UART was previously release before all bits of the
last byte were shifted out. This adds a busy loop waiting while the
peripheral is still busy, fixing the issue.

Co-authored-by: benpicco <benpicco@googlemail.com>
This commit is contained in:
Marian Buschsieweke 2024-04-14 16:15:44 +02:00
parent 3cdc4379b7
commit f4baa0f2e1
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1 changed files with 7 additions and 0 deletions
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7
cpu/msp430/periph/uart_usci.c
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@ -1,5 +1,6 @@
/*
* Copyright (C) 2015 Freie Universität Berlin
* 2024 Marian Buschsieweke
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
@ -15,6 +16,7 @@
* @brief Low-level UART driver implementation
*
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
* @author Marian Buschsieweke <marian.buschsieweke@posteo.net>
*
* @}
*/
@ -130,6 +132,11 @@ void uart_write(uart_t uart, const uint8_t *data, size_t len)
usci->dev->TXBUF = *data++;
}
while (usci->dev->STAT & UCBUSY) {
/* busy wait for completion, e.g. to avoid losing chars/bits
* before releasing the USCI in TX only mode. */
}
if (tx_only) {
msp430_usci_release(usci);
}