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added spark core board

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This commit is contained in:
Christian Mehlis 2014-09-17 15:08:57 +02:00
parent d28c588652
commit f3b1753ac7
12 changed files with 769 additions and 5 deletions
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3
boards/spark-core/Makefile Normal file
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MODULE =$(BOARD)_base
include $(RIOTBASE)/Makefile.base

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boards/spark-core/Makefile.include Normal file
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## the cpu to build for
export CPU = stm32f1
export CPU_MODEL = stm32f103cb
# set the default port
export PORT ?= /dev/ttyUSB0
export BINFILE = $(patsubst %.elf,%.bin,$(ELFFILE))
# define tools used for building the project
export PREFIX = arm-none-eabi-
export CC = $(PREFIX)gcc
export AR = $(PREFIX)ar
export AS = $(PREFIX)as
export LINK = $(PREFIX)gcc
export SIZE = $(PREFIX)size
export OBJCOPY = $(PREFIX)objcopy
export TERMPROG = $(RIOTBASE)/dist/tools/pyterm/pyterm
export FLASHER = $(OBJCOPY) -O binary $(ELFFILE) $(BINFILE) ; dfu-util -d 1d50:607f -a 0 -s 0x08005000:leave -D "$(BINFILE)"
export DEBUGGER = # spark core has no debugger
export RESET = # dfu-util has no support for resetting the device
# define build specific options
export CPU_USAGE = -mcpu=cortex-m3
export FPU_USAGE =
export CFLAGS += -ggdb -g3 -std=gnu99 -Os -Wall -Wstrict-prototypes $(CPU_USAGE) $(FPU_USAGE) -mlittle-endian -mthumb -mthumb-interwork -nostartfiles
export CFLAGS += -ffunction-sections -fdata-sections -fno-builtin
export ASFLAGS += -ggdb -g3 $(CPU_USAGE) $(FPU_USAGE) -mlittle-endian
export LINKFLAGS += -ggdb -g3 -std=gnu99 $(CPU_USAGE) $(FPU_USAGE) -mlittle-endian -static -lgcc -mthumb -mthumb-interwork -nostartfiles
# $(LINKERSCRIPT) is specified in cpu/Makefile.include
export LINKFLAGS += -T$(LINKERSCRIPT)
export OFLAGS = -O ihex
export FFLAGS = $(HEXFILE)
export DEBUGGER_FLAGS = $(RIOTBOARD)/$(BOARD)/dist/gdb.conf $(ELFFILE)
export TERMFLAGS = -p $(PORT)
# use the nano-specs of the NewLib when available
ifeq ($(shell $(LINK) -specs=nano.specs -E - 2>/dev/null >/dev/null </dev/null ; echo $$?),0)
export LINKFLAGS += -specs=nano.specs -lc -lnosys
endif
# export board specific includes to the global includes-listing
export INCLUDES += -I$(RIOTBOARD)/$(BOARD)/include/ -I$(RIOTBASE)/drivers/at86rf231/include -I$(RIOTBASE)/sys/net/include

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boards/spark-core/board.c Normal file
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/*
* Copyright (C) 2014 Freie Universität Berlin
*
* This file is subject to the terms and conditions of the GNU Lesser General
* Public License v2.1. See the file LICENSE in the top level directory for more
* details.
*/
/**
* @ingroup board_spark-core
* @{
*
* @file board.c
* @brief Board specific implementations for the spark-core board
*
* @author Christian Mehlis <mehlis@inf.fu-berlin.de>
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
*
* @}
*/
#include "board.h"
#include "cpu.h"
static void leds_init(void);
void board_init(void)
{
/* initialize the CPU */
cpu_init();
/* initialize the boards LEDs */
leds_init();
/* disable systick interrupt, set by the spark bootloader */
SysTick->CTRL = 0;
/* signal to spark bootloader: do not enable IWDG! set Stop Mode Flag! */
BKP->DR9 = 0xAFFF;
/* configure the RIOT vector table location to internal flash + spark bootloader offset */
SCB->VTOR = LOCATION_VTABLE;
}
/**
* @brief Initialize the boards on-board LEDs
*
* The LEDs initialization is hard-coded in this function. As the LED is soldered
* onto the board it is fixed to its CPU pins.
*
*/
static void leds_init(void)
{
/* enable clock for port A */
RCC->APB2ENR |= RCC_APB2ENR_IOPAEN;
/* reset pins */
LED_PORT->CRH &= ~(0xf << (4*(LED_RED_PIN - 8)) |
0xf << (4*(LED_GREEN_PIN - 8)) |
0xf << (4*(LED_BLUE_PIN - 8)) |
0xf << (4*(LED_WHITE_PIN - 8)));
/* set pins to out */
LED_PORT->CRH |= (0x3 << (4*(LED_RED_PIN - 8)) |
0x3 << (4*(LED_GREEN_PIN - 8)) |
0x3 << (4*(LED_BLUE_PIN - 8)) |
0x3 << (4*(LED_WHITE_PIN - 8)));
LED_PORT->BSRR = (1 << LED_RED_PIN) | (1 << LED_GREEN_PIN) | (1 << LED_BLUE_PIN) | (1 << LED_WHITE_PIN);
}

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/*
* Copyright (C) 2014 Freie Universität Berlin
*
* This file is subject to the terms and conditions of the GNU Lesser General
* Public License v2.1. See the file LICENSE in the top level directory for more
* details.
*/
/**
* @defgroup board_spark-core Spark-Core
* @ingroup boards
* @brief Board specific files for the spark-core board.
* @{
*
* @file
* @brief Board specific definitions for the spark-core board.
*
* @author Christian Mehlis <mehlis@inf.fu-berlin.de>
*/
#ifndef BOARD_H_
#define BOARD_H_
#include <stdint.h>
#include "cpu.h"
#include "periph_conf.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @name Define the nominal CPU core clock in this board
*/
#define F_CPU CLOCK_CORECLOCK
/**
* @name Define the location of the RIOT image in flash
*/
#define LOCATION_VTABLE (0x08005000)
/**
* @name Define the UART to be used as stdio and its baudrate
* @{
*/
#define STDIO UART_0
#define STDIO_BAUDRATE (115200)
#define STDIO_RX_BUFSIZE (64U)
/** @} */
/**
* @name Assign the hardware timer
*/
#define HW_TIMER TIMER_0
/**
* @name LED pin definitions
* @{
*/
#define LED_PORT (GPIOA)
#define LED_RED_PIN (9)
#define LED_GREEN_PIN (10)
#define LED_BLUE_PIN (8)
#define LED_WHITE_PIN (13)
/** @} */
/**
* @name Macros for controlling the on-board LEDs.
* @{
*/
#define LED_RED_ON (LED_PORT->BRR = (1<<LED_RED_PIN))
#define LED_RED_OFF (LED_PORT->BSRR = (1<<LED_RED_PIN))
#define LED_RED_TOGGLE (LED_PORT->ODR ^= (1<<LED_RED_PIN))
#define LED_GREEN_ON (LED_PORT->BRR = (1<<LED_GREEN_PIN))
#define LED_GREEN_OFF (LED_PORT->BSRR = (1<<LED_GREEN_PIN))
#define LED_GREEN_TOGGLE (LED_PORT->ODR ^= (1<<LED_GREEN_PIN))
#define LED_BLUE_ON (LED_PORT->BRR = (1<<LED_BLUE_PIN))
#define LED_BLUE_OFF (LED_PORT->BSRR = (1<<LED_BLUE_PIN))
#define LED_BLUE_TOGGLE (LED_PORT->ODR ^= (1<<LED_BLUE_PIN))
#define LED_WHITE_ON (LED_PORT->BRR = (1<<LED_WHITE_PIN))
#define LED_WHITE_OFF (LED_PORT->BSRR = (1<<LED_WHITE_PIN))
#define LED_WHITE_TOGGLE (LED_PORT->ODR ^= (1<<LED_WHITE_PIN))
/** @} */
/**
* @name User button configuration
*/
#define BUTTON1 GPIO_0
/**
* @name CC3000 pin configuration
* @{
*/
#define CC3000_SPI SPI_0
#define CC3000_CS GPIO_1
#define CC3000_EN GPIO_2
#define CC3000_INT GPIO_3
/** @} */
/**
* @name EXTFLASH pin configuration
* @{
*/
#define EXTFLASH_SPI SPI_0
#define EXTFLASH GPIO_4
/** @} */
/**
* Define the type for the radio packet length for the transceiver
*/
typedef uint8_t radio_packet_length_t;
/**
* @brief Initialize board specific hardware, including clock, LEDs and std-IO
*/
void board_init(void);
#ifdef __cplusplus
} /* end extern "C" */
#endif
#endif /* BOARD_H_ */
/** @} */

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boards/spark-core/include/periph_conf.h Normal file
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/*
* Copyright (C) 2014 Freie Universität Berlin
*
* This file is subject to the terms and conditions of the GNU Lesser General
* Public License v2.1. See the file LICENSE in the top level directory for more
* details.
*/
/**
* @ingroup board_spark-core
* @{
*
* @file periph_conf.h
* @brief Peripheral MCU configuration for the spark-core board
*
* @author Christian Mehlis <mehlis@inf.fu-berlin.de>
*/
#ifndef __PERIPH_CONF_H
#define __PERIPH_CONF_H
#ifdef __cplusplus
extern "C" {
#endif
/**
* @name Clock system configuration
* @{
**/
#define CLOCK_HSE (16000000U) /* frequency of external oscillator */
#define CLOCK_CORECLOCK (72000000U) /* targeted core clock frequency */
/* configuration of PLL prescaler and multiply values */
/* CORECLOCK := HSE / PLL_HSE_DIV * PLL_HSE_MUL */
#define CLOCK_PLL_HSE_DIV RCC_CFGR_PLLXTPRE_HSE
#define CLOCK_PLL_HSE_MUL RCC_CFGR_PLLMULL9
/* configuration of peripheral bus clock prescalers */
#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1 /* AHB clock -> 72MHz */
#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* APB2 clock -> 72MHz */
#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2 /* APB1 clock -> 36MHz */
/* configuration of flash access cycles */
#define CLOCK_FLASH_LATENCY FLASH_ACR_LATENCY_2
/** @} */
/**
* @brief Timer configuration
* @{
*/
#define TIMER_NUMOF (2U)
#define TIMER_0_EN 1
#define TIMER_1_EN 1
/* Timer 0 configuration */
#define TIMER_0_DEV_0 TIM2
#define TIMER_0_DEV_1 TIM3
#define TIMER_0_CHANNELS 4
#define TIMER_0_PRESCALER (72U)
#define TIMER_0_MAX_VALUE (0xffff)
#define TIMER_0_CLKEN() (RCC->APB1ENR |= (RCC_APB1ENR_TIM2EN | RCC_APB1ENR_TIM3EN))
#define TIMER_0_ISR_0 isr_tim2
#define TIMER_0_ISR_1 isr_tim3
#define TIMER_0_IRQ_CHAN_0 TIM2_IRQn
#define TIMER_0_IRQ_CHAN_1 TIM3_IRQn
#define TIMER_0_IRQ_PRIO 1
#define TIMER_0_TRIG_SEL TIM_SMCR_TS_0
/* Timer 1 configuration */
#define TIMER_1_DEV_0 TIM4
#define TIMER_1_DEV_1 TIM5
#define TIMER_1_CHANNELS 4
#define TIMER_1_PRESCALER (36000U)
#define TIMER_1_MAX_VALUE (0xffff)
#define TIMER_1_CLKEN() (RCC->APB1ENR |= (RCC_APB1ENR_TIM4EN | RCC_APB1ENR_TIM5EN))
#define TIMER_1_ISR_0 isr_tim4
#define TIMER_1_ISR_1 isr_tim5
#define TIMER_1_IRQ_CHAN_0 TIM4_IRQn
#define TIMER_1_IRQ_CHAN_1 TIM5_IRQn
#define TIMER_1_IRQ_PRIO 1
#define TIMER_1_TRIG_SEL TIM_SMCR_TS_1
/** @} */
/**
* @brief UART configuration
*/
#define UART_NUMOF (1U)
#define UART_0_EN 1
#define UART_IRQ_PRIO 1
/* UART 0 device configuration */
#define UART_0_DEV USART2
#define UART_0_CLKEN() (RCC->APB1ENR |= RCC_APB1ENR_USART2EN)
#define UART_0_IRQ USART2_IRQn
#define UART_0_ISR isr_usart2
#define UART_0_BUS_FREQ (72000000/4)
/* UART 0 pin configuration */
#define UART_0_PORT GPIOA
#define UART_0_PORT_CLKEN() (RCC->APB2ENR |= RCC_APB2ENR_IOPAEN)
#define UART_0_RX_PIN 3
#define UART_0_TX_PIN 2
#define UART_0_AF 0
/**
* @brief GPIO configuration
*/
#define GPIO_NUMOF (13U)
#define GPIO_0_EN 1
#define GPIO_1_EN 1
#define GPIO_2_EN 1
#define GPIO_3_EN 1
#define GPIO_4_EN 1
#define GPIO_5_EN 1
#define GPIO_6_EN 1
#define GPIO_7_EN 1
#define GPIO_8_EN 1
#define GPIO_9_EN 1
#define GPIO_10_EN 1
#define GPIO_11_EN 1
#define GPIO_12_EN 1
#define GPIO_IRQ_PRIO 1
/* IRQ config */
#define GPIO_IRQ_0 0 /* not used */
#define GPIO_IRQ_1 0 /* not used */
#define GPIO_IRQ_2 GPIO_0
#define GPIO_IRQ_3 GPIO_9
#define GPIO_IRQ_4 GPIO_8
#define GPIO_IRQ_5 GPIO_7
#define GPIO_IRQ_6 GPIO_6
#define GPIO_IRQ_7 GPIO_5
#define GPIO_IRQ_8 GPIO_2
#define GPIO_IRQ_9 GPIO_4
#define GPIO_IRQ_10 0 /* not used */
#define GPIO_IRQ_11 GPIO_3
#define GPIO_IRQ_12 GPIO_1
#define GPIO_IRQ_13 GPIO_12
#define GPIO_IRQ_14 GPIO_11
#define GPIO_IRQ_15 GPIO_10
/* GPIO channel 0 config */
#define GPIO_0_PORT GPIOB /* Used for user button 1 */
#define GPIO_0_PIN 2
#define GPIO_0_CLKEN() (RCC->APB2ENR |= RCC_APB2ENR_IOPBEN)
#define GPIO_0_EXTI_CFG() (AFIO->EXTICR[0] |= AFIO_EXTICR1_EXTI2_PB)
#define GPIO_0_EXTI_LINE 2
#define GPIO_0_IRQ EXTI4_IRQn
/* GPIO channel 1 config */
#define GPIO_1_PORT GPIOB /* Used for CC3000 CS */
#define GPIO_1_PIN 12
#define GPIO_1_CLKEN() (RCC->APB2ENR |= RCC_APB2ENR_IOPBEN)
#define GPIO_1_EXTI_CFG() (AFIO->EXTICR[3] |= AFIO_EXTICR4_EXTI12_PB)
#define GPIO_1_EXTI_LINE 12
#define GPIO_1_IRQ EXTI4_IRQn
/* GPIO channel 2 config */
#define GPIO_2_PORT GPIOB /* Used for CC3000 EN */
#define GPIO_2_PIN 8
#define GPIO_2_CLKEN() (RCC->APB2ENR |= RCC_APB2ENR_IOPBEN)
#define GPIO_2_EXTI_CFG() (AFIO->EXTICR[2] |= AFIO_EXTICR3_EXTI8_PB)
#define GPIO_2_EXTI_LINE 8
#define GPIO_2_IRQ EXTI4_IRQn
/* GPIO channel 3 config */
#define GPIO_3_PORT GPIOB /* Used for CC3000 INT */
#define GPIO_3_PIN 11
#define GPIO_3_CLKEN() (RCC->APB2ENR |= RCC_APB2ENR_IOPBEN)
#define GPIO_3_EXTI_CFG() (AFIO->EXTICR[2] |= AFIO_EXTICR3_EXTI11_PB)
#define GPIO_3_EXTI_LINE 11
#define GPIO_3_IRQ EXTI4_IRQn
/* GPIO channel 4 config */
#define GPIO_4_PORT GPIOB /* Used for EXTFLASH CS */
#define GPIO_4_PIN 9
#define GPIO_4_CLKEN() (RCC->APB2ENR |= RCC_APB2ENR_IOPBEN)
#define GPIO_4_EXTI_CFG() (AFIO->EXTICR[2] |= AFIO_EXTICR3_EXTI9_PB)
#define GPIO_4_EXTI_LINE 9
#define GPIO_4_IRQ EXTI4_IRQn
/* GPIO channel 5 config */
#define GPIO_5_PORT GPIOB /* D0 */
#define GPIO_5_PIN 7
#define GPIO_5_CLKEN() (RCC->APB2ENR |= RCC_APB2ENR_IOPBEN)
#define GPIO_5_EXTI_CFG() (AFIO->EXTICR[1] |= AFIO_EXTICR2_EXTI7_PB)
#define GPIO_5_EXTI_LINE 7
#define GPIO_5_IRQ EXTI4_IRQn
/* GPIO channel 6 config */
#define GPIO_6_PORT GPIOB /* D1 */
#define GPIO_6_PIN 6
#define GPIO_6_CLKEN() (RCC->APB2ENR |= RCC_APB2ENR_IOPBEN)
#define GPIO_6_EXTI_CFG() (AFIO->EXTICR[1] |= AFIO_EXTICR2_EXTI6_PB)
#define GPIO_6_EXTI_LINE 6
#define GPIO_6_IRQ EXTI3_IRQn
/* GPIO channel 7 config */
#define GPIO_7_PORT GPIOB /* D2 */
#define GPIO_7_PIN 5
#define GPIO_7_CLKEN() (RCC->APB2ENR |= RCC_APB2ENR_IOPBEN)
#define GPIO_7_EXTI_CFG() (AFIO->EXTICR[1] |= AFIO_EXTICR2_EXTI5_PB)
#define GPIO_7_EXTI_LINE 5
#define GPIO_7_IRQ EXTI3_IRQn
/* GPIO channel 8 config */
#define GPIO_8_PORT GPIOB /* D3 */
#define GPIO_8_PIN 4
#define GPIO_8_CLKEN() (RCC->APB2ENR |= RCC_APB2ENR_IOPBEN)
#define GPIO_8_EXTI_CFG() (AFIO->EXTICR[1] |= AFIO_EXTICR2_EXTI4_PB)
#define GPIO_8_EXTI_LINE 4
#define GPIO_8_IRQ EXTI4_IRQn
/* GPIO channel 9 config */
#define GPIO_9_PORT GPIOB /* D4 */
#define GPIO_9_PIN 3
#define GPIO_9_CLKEN() (RCC->APB2ENR |= RCC_APB2ENR_IOPBEN)
#define GPIO_9_EXTI_CFG() (AFIO->EXTICR[0] |= AFIO_EXTICR1_EXTI3_PB)
#define GPIO_9_EXTI_LINE 3
#define GPIO_9_IRQ EXTI4_IRQn
/* GPIO channel 10 config */
#define GPIO_10_PORT GPIOA /* D5 */
#define GPIO_10_PIN 15
#define GPIO_10_CLKEN() (RCC->APB2ENR |= RCC_APB2ENR_IOPAEN)
#define GPIO_10_EXTI_CFG() (AFIO->EXTICR[3] |= AFIO_EXTICR4_EXTI15_PA)
#define GPIO_10_EXTI_LINE 15
#define GPIO_10_IRQ EXTI4_IRQn
/* GPIO channel 11 config */
#define GPIO_11_PORT GPIOA /* D6 */
#define GPIO_11_PIN 14
#define GPIO_11_CLKEN() (RCC->APB2ENR |= RCC_APB2ENR_IOPAEN)
#define GPIO_11_EXTI_CFG() (AFIO->EXTICR[3] |= AFIO_EXTICR4_EXTI14_PA)
#define GPIO_11_EXTI_LINE 14
#define GPIO_11_IRQ EXTI4_IRQn
/* GPIO channel 12 config */
#define GPIO_12_PORT GPIOA /* D7 */
#define GPIO_12_PIN 13
#define GPIO_12_CLKEN() (RCC->APB2ENR |= RCC_APB2ENR_IOPAEN)
#define GPIO_12_EXTI_CFG() (AFIO->EXTICR[3] |= AFIO_EXTICR4_EXTI13_PA)
#define GPIO_12_EXTI_LINE 13
#define GPIO_12_IRQ EXTI4_IRQn
/**
* @brief SPI configuration
* @{
*/
#define SPI_NUMOF (1U)
#define SPI_0_EN 1
/* SPI 0 device configuration */
#define SPI_0_DEV SPI1
#define SPI_0_CLKEN() (RCC->APB2ENR |= RCC_APB2ENR_SPI1EN)
#define SPI_0_CLKDIS() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
#define SPI_0_BUS_DIV 0 /* 1 -> SPI runs with full CPU clock, 0 -> half CPU clock */
/* SPI 0 pin configuration */
#define SPI_0_CLK_PORT GPIOB
#define SPI_0_CLK_PIN 15
#define SPI_0_CLK_PORT_CLKEN() (RCC->APB2ENR |= RCC_APB2ENR_IOPBEN)
#define SPI_0_MOSI_PORT GPIOB
#define SPI_0_MOSI_PIN 17
#define SPI_0_MOSI_PORT_CLKEN() (RCC->APB2ENR |= RCC_APB2ENR_IOPBEN)
#define SPI_0_MISO_PORT GPIOB
#define SPI_0_MISO_PIN 16
#define SPI_0_MISO_PORT_CLKEN() (RCC->APB2ENR |= RCC_APB2ENR_IOPBEN)
/** @} */
#ifdef __cplusplus
} /* end extern "C" */
#endif
#endif /* __PERIPH_CONF_H */
/** @} */

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/*
* Copyright (C) 2014 Freie Universität Berlin
*
* This file is subject to the terms and conditions of the GNU Lesser General
* Public License v2.1. See the file LICENSE in the top level directory for more
* details.
*/
/**
* @ingroup board_iot-lab_M3
* @{
*
* @file system_stm32f1.c
* @brief Board specific clock setup
*
* @author Thomas Eichinger <thomas.eichinger@fu-berlin.de>
*
* @}
*/
#include "stm32f10x.h"
#include "board.h"
uint32_t SystemCoreClock = F_CPU;
#define VECT_TAB_OFFSET 0x0
static void set_system_clock(void)
{
volatile uint32_t startup_counter = 0, HSE_status = 0;
/* SYSCLK, HCLK, PCLK2 and PCLK1 configuration */
/* Enable HSE */
RCC->CR |= ((uint32_t)RCC_CR_HSEON);
/* Wait till HSE is ready and if Time out is reached exit */
do {
HSE_status = RCC->CR & RCC_CR_HSERDY;
startup_counter++;
}
while ((HSE_status == 0) && (startup_counter != HSE_STARTUP_TIMEOUT));
if ((RCC->CR & RCC_CR_HSERDY) != RESET) {
HSE_status = (uint32_t)0x01;
}
else {
HSE_status = (uint32_t)0x00;
}
if (HSE_status == (uint32_t)0x01) {
/* Enable Prefetch Buffer */
FLASH->ACR |= FLASH_ACR_PRFTBE;
/* Flash 2 wait state */
FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
/* HCLK = SYSCLK */
RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
/* PCLK2 = HCLK */
RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
/* PCLK1 = HCLK */
RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
/* NOTE : agilefox : modified to take into account the 16MHz
crystal instead of 8MHz */
/* PLL configuration: PLLCLK = HSE / 2 * 9 = 72 MHz */
RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC
| RCC_CFGR_PLLXTPRE
| RCC_CFGR_PLLMULL));
RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE
| RCC_CFGR_PLLXTPRE_HSE_Div2
| RCC_CFGR_PLLMULL9);
/* Enable PLL */
RCC->CR |= RCC_CR_PLLON;
/* Wait till PLL is ready */
while ((RCC->CR & RCC_CR_PLLRDY) == 0) {
}
/* Select PLL as system clock source */
RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
/* Wait till PLL is used as system clock source */
while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) {
}
}
else {
/* If HSE fails to start-up, the application will have wrong clock
configuration. User can add here some code to deal with this error */
}
}
void SystemInit(void)
{
/* Reset the RCC clock configuration to the default reset state(for debug purpose) */
/* Set HSION bit */
RCC->CR |= (uint32_t)0x00000001;
/* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
RCC->CFGR &= (uint32_t)0xF0FF0000;
/* Reset HSEON, CSSON and PLLON bits */
RCC->CR &= (uint32_t)0xFEF6FFFF;
/* Reset HSEBYP bit */
RCC->CR &= (uint32_t)0xFFFBFFFF;
/* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
RCC->CFGR &= (uint32_t)0xFF80FFFF;
/* Disable all interrupts and clear pending bits */
RCC->CIR = 0x009F0000;
/* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
/* Configure the Flash Latency cycles and enable prefetch buffer */
set_system_clock();
/* Vector Table Relocation in Internal FLASH. */
SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET;
}

142
cpu/stm32f1/stm32f103cb_linkerscript.ld Normal file
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/* ----------------------------------------------------------------------------
* SAM Software Package License
* ----------------------------------------------------------------------------
* Copyright (c) 2012, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following condition is met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/*OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
OUTPUT_ARCH(arm)
SEARCH_DIR(.)*/
/* Memory Spaces Definitions */
MEMORY
{
rom (rx) : ORIGIN = 0x08005000, LENGTH = 128K-0x5000
ram (xrw) : ORIGIN = 0x20000000, LENGTH = 20K
}
/* The stack size used by the application. NOTE: you need to adjust */
STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x200 ;
/* Section Definitions */
SECTIONS
{
.text :
{
. = ALIGN(4);
_sfixed = .;
KEEP(*(.vectors .vectors.*))
*(.text .text.* .gnu.linkonce.t.*)
*(.glue_7t) *(.glue_7)
*(.rodata .rodata* .gnu.linkonce.r.*)
*(.ARM.extab* .gnu.linkonce.armextab.*)
/* Support C constructors, and C destructors in both user code
and the C library. This also provides support for C++ code. */
. = ALIGN(4);
KEEP(*(.init))
. = ALIGN(4);
__preinit_array_start = .;
KEEP (*(.preinit_array))
__preinit_array_end = .;
. = ALIGN(4);
__init_array_start = .;
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array))
__init_array_end = .;
. = ALIGN(0x4);
KEEP (*crtbegin.o(.ctors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*crtend.o(.ctors))
. = ALIGN(4);
KEEP(*(.fini))
. = ALIGN(4);
__fini_array_start = .;
KEEP (*(.fini_array))
KEEP (*(SORT(.fini_array.*)))
__fini_array_end = .;
KEEP (*crtbegin.o(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*crtend.o(.dtors))
. = ALIGN(4);
_efixed = .; /* End of text section */
} > rom
/* .ARM.exidx is sorted, so has to go in its own output section. */
PROVIDE_HIDDEN (__exidx_start = .);
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > rom
PROVIDE_HIDDEN (__exidx_end = .);
. = ALIGN(4);
_etext = .;
.relocate : AT (_etext)
{
. = ALIGN(4);
_srelocate = .;
*(.ramfunc .ramfunc.*);
*(.data .data.*);
. = ALIGN(4);
_erelocate = .;
} > ram
/* .bss section which is used for uninitialized data */
.bss (NOLOAD) :
{
. = ALIGN(4);
_sbss = . ;
_szero = .;
*(.bss .bss.*)
*(COMMON)
. = ALIGN(4);
_ebss = . ;
_ezero = .;
} > ram
/* stack section */
.stack (NOLOAD) :
{
. = ALIGN(4);
_sstack = .;
. = . + STACK_SIZE;
. = ALIGN(4);
_estack = .;
} > ram
. = ALIGN(4);
_end = . ;
}

2
examples/riot_and_cpp/Makefile
View File

@ -31,7 +31,7 @@ QUIET ?= 1
BOARD_BLACKLIST := arduino-due avsextrem chronos mbed_lpc1768 msb-430h msba2 redbee-econotag \
telosb wsn430-v1_3b wsn430-v1_4 msb-430 pttu udoo qemu-i386 z1 stm32f0discovery \
stm32f3discovery stm32f4discovery pca10000 pca10005 iot-lab_M3 arduino-mega2560 \
msbiot yunjia-nrf51822 samr21-xpro cc2538dk openmote
msbiot yunjia-nrf51822 samr21-xpro cc2538dk openmote spark-core
# This example only works with native for now.
# msb430-based boards: msp430-g++ is not provided in mspgcc.

3
tests/bloom/Makefile
View File

@ -2,7 +2,8 @@ APPLICATION = bloom
include ../Makefile.tests_common
BOARD_INSUFFICIENT_RAM := chronos msb-430 msb-430h redbee-econotag \
telosb wsn430-v1_3b wsn430-v1_4 z1 stm32f0discovery
telosb wsn430-v1_3b wsn430-v1_4 z1 stm32f0discovery \
spark-core
BOARD_BLACKLIST := arduino-mega2560
# arduino-mega2560: Errors in assembly, e.g:

2
tests/posix_semaphore/Makefile
View File

@ -2,7 +2,7 @@ APPLICATION = posix_semaphore
include ../Makefile.tests_common
BOARD_INSUFFICIENT_RAM := msb-430 msb-430h mbed_lpc1768 redbee-econotag chronos stm32f0discovery \
pca10000 pca10005 yunjia-nrf51822
pca10000 pca10005 yunjia-nrf51822 spark-core
USEMODULE += posix

2
tests/pthread_rwlock/Makefile
View File

@ -13,6 +13,6 @@ DISABLE_MODULE += auto_init
CFLAGS += -DNATIVE_AUTO_EXIT
BOARD_INSUFFICIENT_RAM += chronos mbed_lpc1768 msb-430 msb-430h stm32f0discovery \
pca10000 pca10005 yunjia-nrf51822
pca10000 pca10005 yunjia-nrf51822 spark-core
include $(RIOTBASE)/Makefile.include

2
tests/thread_cooperation/Makefile
View File

@ -2,7 +2,7 @@ APPLICATION = thread_cooperation
include ../Makefile.tests_common
BOARD_INSUFFICIENT_RAM := chronos msb-430 msb-430h mbed_lpc1768 redbee-econotag stm32f0discovery \
pca10000 pca10005 yunjia-nrf51822
pca10000 pca10005 yunjia-nrf51822 spark-core
DISABLE_MODULE += auto_init