diff --git a/cpu/cc26x0/include/cc26x0_prcm.h b/cpu/cc26x0/include/cc26x0_prcm.h
index 53947cfbc4..60683c40f3 100644
--- a/cpu/cc26x0/include/cc26x0_prcm.h
+++ b/cpu/cc26x0/include/cc26x0_prcm.h
@@ -202,6 +202,40 @@ typedef struct {
 
 #define AON_WUC ((aon_wuc_regs_t *) (AON_WUC_BASE)) /**< AON_WUC register bank */
 
+/**
+ * AON_RTC registers
+ */
+typedef struct {
+    reg32_t CTL; /**< Control */
+    reg32_t EVFLAGS; /**< Event Flags, RTC Status */
+    reg32_t SEC; /**< Second Counter Value, Integer Part */
+    reg32_t SUBSEC; /**< Second Counter Value, Fractional Part */
+    reg32_t SUBSECINC; /**< Subseconds Increment */
+    reg32_t CHCTL; /**< Channel Configuration */
+    reg32_t CH0CMP; /**< Channel 0 Compare Value */
+    reg32_t CH1CMP; /**< Channel 1 Compare Value */
+    reg32_t CH2CMP; /**< Channel 2 Compare Value */
+    reg32_t CH2CMPINC; /**< Channel 2 Compare Value Auto-increment */
+    reg32_t CH1CAPT; /**< Channel 1 Capture Value */
+    reg32_t SYNC; /**< AON Synchronization */
+} aon_rtc_regs_t;
+
+/**
+ * @brief   RTC_UPD is a 16 KHz signal used to sync up the radio timer. The
+ *          16 Khz is SCLK_LF divided by 2
+ * @details 0h = RTC_UPD signal is forced to 0
+ *          1h = RTC_UPD signal is toggling @16 kHz
+ */
+#define AON_RTC_CTL_RTC_UPD_EN 0x00000002
+
+/** @ingroup cpu_specific_peripheral_memory_map
+  * @{
+  */
+#define AON_RTC_BASE (PERIPH_BASE + 0x92000) /**< AON_RTC base address */
+/** @} */
+
+#define AON_RTC ((aon_rtc_regs_t *) (AON_RTC_BASE)) /**< AON_RTC register bank */
+
 
 /**
  * PRCM registers