diff --git a/boards/nucleo-wl55jc/include/periph_conf.h b/boards/nucleo-wl55jc/include/periph_conf.h
index 7dcc5c6e59..e5d82ea71e 100644
--- a/boards/nucleo-wl55jc/include/periph_conf.h
+++ b/boards/nucleo-wl55jc/include/periph_conf.h
@@ -35,6 +35,7 @@
 
 #include "periph_cpu.h"
 #include "clk_conf.h"
+#include "cfg_rtt_default.h"
 #include "cfg_timer_tim2.h"
 
 #ifdef __cplusplus
diff --git a/cpu/stm32/periph/rtt_all.c b/cpu/stm32/periph/rtt_all.c
index 9e4ff785ab..167590a034 100644
--- a/cpu/stm32/periph/rtt_all.c
+++ b/cpu/stm32/periph/rtt_all.c
@@ -79,7 +79,7 @@ register. */
 #if defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32WB)
 #define IMR_REG             IMR2
 #define EXTI_IMR_BIT        EXTI_IMR2_IM32
-#elif defined(CPU_FAM_STM32G0)
+#elif defined(CPU_FAM_STM32G0) || defined(CPU_FAM_STM32WL)
 #define IMR_REG             IMR1
 #define EXTI_IMR_BIT        EXTI_IMR1_IM29
 #elif defined(CPU_FAM_STM32G4)
@@ -108,7 +108,9 @@ static void *to_arg;
 
 void rtt_init(void)
 {
+    /* Enable the low speed clock (LSE) */
     stmclk_enable_lfclk();
+
     /* power on the selected LPTIMER */
     rtt_poweron();
 
@@ -128,7 +130,7 @@ void rtt_init(void)
     EXTI->IMR_REG |= EXTI_IMR_BIT;
 #if !defined(CPU_FAM_STM32L4) && !defined(CPU_FAM_STM32L0) && \
     !defined(CPU_FAM_STM32WB) && !defined(CPU_FAM_STM32G4) && \
-    !defined(CPU_FAM_STM32G0)
+    !defined(CPU_FAM_STM32G0) && !defined(CPU_FAM_STM32WL)
     EXTI->FTSR_REG &= ~(EXTI_FTSR_BIT);
     EXTI->RTSR_REG |= EXTI_RTSR_BIT;
     EXTI->PR_REG = EXTI_PR_BIT;
@@ -239,7 +241,7 @@ void isr_lptim1(void)
     LPTIM1->ICR = (LPTIM_ICR_ARRMCF | LPTIM_ICR_CMPMCF);
 #if !defined(CPU_FAM_STM32L4) && !defined(CPU_FAM_STM32L0) && \
     !defined(CPU_FAM_STM32WB) && !defined(CPU_FAM_STM32G4) && \
-    !defined(CPU_FAM_STM32G0)
+    !defined(CPU_FAM_STM32G0) && !defined(CPU_FAM_STM32WL)
     EXTI->PR_REG = EXTI_PR_BIT; /* only clear the associated bit */
 #endif
 
diff --git a/cpu/stm32/stmclk/stmclk_common.c b/cpu/stm32/stmclk/stmclk_common.c
index 71cb4e8ac0..00301139c3 100644
--- a/cpu/stm32/stmclk/stmclk_common.c
+++ b/cpu/stm32/stmclk/stmclk_common.c
@@ -71,6 +71,13 @@ void stmclk_enable_lfclk(void)
         stmclk_dbp_unlock();
         RCC->REG_LSE |= BIT_LSEON;
         while (!(RCC->REG_LSE & BIT_LSERDY)) {}
+
+    /* Set LSE system clock enable bit. This is required if LSE is to be used by
+       USARTx, LPUARTx, LPTIMx, TIMx, RNG, system LSCO, MCO, MSI PLL mode */
+#if defined(CPU_FAM_STM32WL)
+        RCC->BDCR |= RCC_BDCR_LSESYSEN;
+        while (!(RCC->BDCR & RCC_BDCR_LSESYSRDY)) {}
+#endif
         stmclk_dbp_lock();
     }
     else {
diff --git a/cpu/stm32/stmclk/stmclk_l4wx.c b/cpu/stm32/stmclk/stmclk_l4wx.c
index e620edc624..cee9b41cb2 100644
--- a/cpu/stm32/stmclk/stmclk_l4wx.c
+++ b/cpu/stm32/stmclk/stmclk_l4wx.c
@@ -606,6 +606,13 @@ void stmclk_init_sysclk(void)
         stmclk_dbp_unlock();
         RCC->BDCR |= RCC_BDCR_LSEON;
         while (!(RCC->BDCR & RCC_BDCR_LSERDY)) {}
+
+    /* Set LSE system clock enable bit. This is required if LSE is to be used by
+       USARTx, LPUARTx, LPTIMx, TIMx, RNG, system LSCO, MCO, MSI PLL mode */
+#if defined(CPU_FAM_STM32WL)
+        RCC->BDCR |= RCC_BDCR_LSESYSEN;
+        while (!(RCC->BDCR & RCC_BDCR_LSESYSRDY)) {}
+#endif
         stmclk_dbp_lock();
     }