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boards/nucleo-f030/70/72: adapt clock configuration

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This commit is contained in:
Alexandre Abadie 2017-08-23 18:13:21 +02:00 committed by Vincent Dupont
parent b81094cf7a
commit eb590c0126
3 changed files with 69 additions and 33 deletions
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34
boards/nucleo-f030/include/periph_conf.h
View File

@ -28,20 +28,32 @@ extern "C" {
#endif
/**
* @name Clock system configuration
* @name Clock settings
*
* @note This is auto-generated from
* `cpu/stm32_common/dist/clk_conf/clk_conf.c`
* @{
*/
#define CLOCK_HSE (8000000U) /* external oscillator */
#define CLOCK_CORECLOCK (48000000U) /* desired core clock frequency */
/* give the target core clock (HCLK) frequency [in Hz],
* maximum: 48MHz */
#define CLOCK_CORECLOCK (48000000U)
/* 0: no external high speed crystal available
* else: actual crystal frequency [in Hz] */
#define CLOCK_HSE (8000000U)
/* 0: no external low speed crystal available,
* 1: external crystal available (always 32.768kHz) */
#define CLOCK_LSE (1)
/* peripheral clock setup */
#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
#define CLOCK_APB1_DIV RCC_CFGR_PPRE_DIV1 /* max 48MHz */
#define CLOCK_APB1 (CLOCK_CORECLOCK / 1)
#define CLOCK_APB2 (CLOCK_APB1)
/* the actual PLL values are automatically generated */
#define CLOCK_PLL_MUL (CLOCK_CORECLOCK / CLOCK_HSE)
/* bus clocks for simplified peripheral initialization, UPDATE MANUALLY! */
#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
#define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
#define CLOCK_APB1 (CLOCK_CORECLOCK / 1)
/** @} */
/* PLL factors */
#define CLOCK_PLL_PREDIV (1)
#define CLOCK_PLL_MUL (6)
/** @} */
/**
* @name Timer configuration

34
boards/nucleo-f070/include/periph_conf.h
View File

@ -28,20 +28,32 @@ extern "C" {
#endif
/**
* @name Clock system configuration
* @name Clock settings
*
* @note This is auto-generated from
* `cpu/stm32_common/dist/clk_conf/clk_conf.c`
* @{
*/
#define CLOCK_HSE (8000000U) /* external oscillator */
#define CLOCK_CORECLOCK (48000000U) /* desired core clock frequency */
/* give the target core clock (HCLK) frequency [in Hz],
* maximum: 48MHz */
#define CLOCK_CORECLOCK (48000000U)
/* 0: no external high speed crystal available
* else: actual crystal frequency [in Hz] */
#define CLOCK_HSE (8000000U)
/* 0: no external low speed crystal available,
* 1: external crystal available (always 32.768kHz) */
#define CLOCK_LSE (1)
/* peripheral clock setup */
#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
#define CLOCK_APB1_DIV RCC_CFGR_PPRE_DIV1 /* max 48MHz */
#define CLOCK_APB1 (CLOCK_CORECLOCK / 1)
#define CLOCK_APB2 (CLOCK_APB1)
/* the actual PLL values are automatically generated */
#define CLOCK_PLL_MUL (CLOCK_CORECLOCK / CLOCK_HSE)
/* bus clocks for simplified peripheral initialization, UPDATE MANUALLY! */
#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
#define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
#define CLOCK_APB1 (CLOCK_CORECLOCK / 1)
/** @} */
/* PLL factors */
#define CLOCK_PLL_PREDIV (1)
#define CLOCK_PLL_MUL (6)
/** @} */
/**
* @name Timer configuration

34
boards/nucleo-f072/include/periph_conf.h
View File

@ -27,20 +27,32 @@ extern "C" {
#endif
/**
* @name Clock system configuration
* @name Clock settings
*
* @note This is auto-generated from
* `cpu/stm32_common/dist/clk_conf/clk_conf.c`
* @{
*/
#define CLOCK_HSE (8000000U) /* external oscillator */
#define CLOCK_CORECLOCK (48000000U) /* desired core clock frequency */
/* give the target core clock (HCLK) frequency [in Hz],
* maximum: 48MHz */
#define CLOCK_CORECLOCK (48000000U)
/* 0: no external high speed crystal available
* else: actual crystal frequency [in Hz] */
#define CLOCK_HSE (8000000U)
/* 0: no external low speed crystal available,
* 1: external crystal available (always 32.768kHz) */
#define CLOCK_LSE (1)
/* peripheral clock setup */
#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
#define CLOCK_APB1_DIV RCC_CFGR_PPRE_DIV1 /* max 48MHz */
#define CLOCK_APB1 (CLOCK_CORECLOCK / 1)
#define CLOCK_APB2 (CLOCK_APB1)
/* the actual PLL values are automatically generated */
#define CLOCK_PLL_MUL (CLOCK_CORECLOCK / CLOCK_HSE)
/* bus clocks for simplified peripheral initialization, UPDATE MANUALLY! */
#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
#define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
#define CLOCK_APB1 (CLOCK_CORECLOCK / 1)
/** @} */
/* PLL factors */
#define CLOCK_PLL_PREDIV (1)
#define CLOCK_PLL_MUL (6)
/** @} */
/**
* @name Timer configuration