diff --git a/boards/stm32l0538-disco/Makefile b/boards/stm32l0538-disco/Makefile new file mode 100644 index 0000000000..f8fcbb53a0 --- /dev/null +++ b/boards/stm32l0538-disco/Makefile @@ -0,0 +1,3 @@ +MODULE = board + +include $(RIOTBASE)/Makefile.base diff --git a/boards/stm32l0538-disco/Makefile.dep b/boards/stm32l0538-disco/Makefile.dep new file mode 100644 index 0000000000..5472bf8b8d --- /dev/null +++ b/boards/stm32l0538-disco/Makefile.dep @@ -0,0 +1,3 @@ +ifneq (,$(filter saul_default,$(USEMODULE))) + USEMODULE += saul_gpio +endif diff --git a/boards/stm32l0538-disco/Makefile.features b/boards/stm32l0538-disco/Makefile.features new file mode 100644 index 0000000000..76233c885d --- /dev/null +++ b/boards/stm32l0538-disco/Makefile.features @@ -0,0 +1,7 @@ +# Put defined MCU peripherals here (in alphabetical order) +FEATURES_PROVIDED += periph_rtc +FEATURES_PROVIDED += periph_spi +FEATURES_PROVIDED += periph_timer +FEATURES_PROVIDED += periph_uart + +-include $(RIOTCPU)/stm32l0/Makefile.features diff --git a/boards/stm32l0538-disco/Makefile.include b/boards/stm32l0538-disco/Makefile.include new file mode 100644 index 0000000000..79ceaa657a --- /dev/null +++ b/boards/stm32l0538-disco/Makefile.include @@ -0,0 +1,18 @@ +# define the cpu used by the stm32l0538-disco board +export CPU = stm32l0 +export CPU_MODEL = stm32l053c8 + +# we use shared STM32 configuration snippets +INCLUDES += -I$(RIOTBOARD)/common/stm32/include + +# define the default port depending on the host OS +PORT_LINUX ?= /dev/ttyUSB0 +PORT_DARWIN ?= $(firstword $(sort $(wildcard /dev/tty.SLAB_USBtoUART*))) + +# setup serial terminal +include $(RIOTMAKE)/tools/serial.inc.mk + +DEBUG_ADAPTER ?= stlink + +# this board uses openocd +include $(RIOTMAKE)/tools/openocd.inc.mk diff --git a/boards/stm32l0538-disco/board.c b/boards/stm32l0538-disco/board.c new file mode 100644 index 0000000000..a1d9fc06e1 --- /dev/null +++ b/boards/stm32l0538-disco/board.c @@ -0,0 +1,32 @@ +/* + * Copyright (C) 2018 Inria + * + * This file is subject to the terms and conditions of the GNU Lesser General + * Public License v2.1. See the file LICENSE in the top level directory for more + * details. + */ + +/** + * @ingroup boards_stm32l0538-disco + * @{ + * + * @file + * @brief Board specific implementations for the STM32L0538-DISCO evaluation board + * + * @author Alexandre Abadie + * + * @} + */ + +#include "board.h" +#include "periph/gpio.h" + +void board_init(void) +{ + /* initialize the boards LEDs */ + gpio_init(LED0_PIN, GPIO_OUT); + gpio_init(LED1_PIN, GPIO_OUT); + + /* initialize the CPU */ + cpu_init(); +} diff --git a/boards/stm32l0538-disco/doc.txt b/boards/stm32l0538-disco/doc.txt new file mode 100644 index 0000000000..d018931a1e --- /dev/null +++ b/boards/stm32l0538-disco/doc.txt @@ -0,0 +1,41 @@ +/** + * @defgroup boards_stm32l0538-disco STM32L0538-DISCO + * @ingroup boards + * @brief Support for the STM32L0538-DISCO board + +### Introduction + +The +[STM32L0538-DISCO](https://www.st.com/en/evaluation-tools/32l0538discovery.html) +discovery kit features an ultra low-power stm32l053c8t6 microcontroller with +64KB of FLASH and 8KB of RAM. +The board also provides an on-board 2.04" E-paper display (not supported yet). + +![STM32L0538-DISCO](https://www.st.com/content/ccc/fragment/product_related/rpn_information/board_photo/group0/67/a2/3f/98/6b/24/4a/27/stm32l0538-discovery.jpg/files/stm32l0538-disco.jpg/_jcr_content/translations/en.stm32l0538-disco.jpg) + +### Supported features + +| Peripheral | Configuration | +|:--------------------- |:----------------------------------------------------------------------------------------- | +| TIMs | TIM2 | +| UARTs | USART1 on PA10 (RX), PA9 (TX) | +| SPIs | SPI1 on PB5 (MOSI), PB4 (MISO), PB3 (SCLK); SPI2 on PB15 (MOSI), PB14 (MISO), PB13 (SCLK) | + +### Flashing the board + +The board can be flashed using OpenOCD via the on-board ST-Link adapter. +Then use the following command: + + make BOARD=stm32l0538-disco -C examples/hello-world flash + +### STDIO + +STDIO is connected to pins PA9 (TX) and PA10 (RX) so an USB to UART adapter is +required. Use the `term` targed to open a terminal: + + make BOARD=stm32l0538-disco -C examples/hello-world term + +If an external ST-Link adapter is used, RX and TX pins can be directly connected +to it. In this case, STDIO is available on /dev/ttyACMx (Linux case). + + */ diff --git a/boards/stm32l0538-disco/include/board.h b/boards/stm32l0538-disco/include/board.h new file mode 100644 index 0000000000..45d8112905 --- /dev/null +++ b/boards/stm32l0538-disco/include/board.h @@ -0,0 +1,75 @@ +/* + * Copyright (C) 2018 Inria + * + * This file is subject to the terms and conditions of the GNU Lesser General + * Public License v2.1. See the file LICENSE in the top level directory for more + * details. + */ + +/** + * @ingroup boards_stm32l0538-disco + * @{ + * + * @file + * @brief Board specific definitions for the STM32L0538-DISCO evaluation board. + * + * @author Alexandre Abadie + */ + +#ifndef BOARD_H +#define BOARD_H + +#include "cpu.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @name Xtimer configuration + * @{ + */ +#define XTIMER_WIDTH (16) +/** @} */ + +/** + * @name Macros for controlling the on-board LEDs. + * @{ + */ +#define LED0_PIN GPIO_PIN(PORT_B, 4) +#define LED0_PORT GPIOB +#define LED0_MASK (1 << 4) + +#define LED0_ON (LED0_PORT->BSRR = LED0_MASK) +#define LED0_OFF (LED0_PORT->BRR = LED0_MASK) +#define LED0_TOGGLE (LED0_PORT->ODR ^= LED0_MASK) + +#define LED1_PIN GPIO_PIN(PORT_A, 5) +#define LED1_PORT GPIOA +#define LED1_MASK (1 << 5) + +#define LED1_ON (LED1_PORT->BSRR = LED1_MASK) +#define LED1_OFF (LED1_PORT->BRR = LED1_MASK) +#define LED1_TOGGLE (LED1_PORT->ODR ^= LED1_MASK) +/** @} */ + +/** + * @name User button + * @{ + */ +#define BTN0_PIN GPIO_PIN(PORT_A, 0) +#define BTN0_PORT GPIOA +#define BTN0_MODE GPIO_IN +/** @} */ + +/** + * @brief Initialize board specific hardware, including clock, LEDs and std-IO + */ +void board_init(void); + +#ifdef __cplusplus +} +#endif + +#endif /* BOARD_H */ +/** @} */ diff --git a/boards/stm32l0538-disco/include/gpio_params.h b/boards/stm32l0538-disco/include/gpio_params.h new file mode 100644 index 0000000000..eab348e274 --- /dev/null +++ b/boards/stm32l0538-disco/include/gpio_params.h @@ -0,0 +1,56 @@ +/* + * Copyright (C) 2018 Inria + * + * This file is subject to the terms and conditions of the GNU Lesser + * General Public License v2.1. See the file LICENSE in the top level + * directory for more details. + */ + +/** + * @ingroup boards_stm32l0538-disco + * @{ + * + * @file + * @brief Board specific configuration of direct mapped GPIOs + * + * @author Alexandre Abadie + */ + +#ifndef GPIO_PARAMS_H +#define GPIO_PARAMS_H + +#include "board.h" +#include "saul/periph.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief GPIO pin configuration + */ +static const saul_gpio_params_t saul_gpio_params[] = +{ + { + .name = "LD3", + .pin = LED0_PIN, + .mode = GPIO_OUT + }, + { + .name = "LD4", + .pin = LED1_PIN, + .mode = GPIO_OUT + }, + { + .name = "BTN USER", + .pin = BTN0_PIN, + .mode = BTN0_MODE + }, +}; + +#ifdef __cplusplus +} +#endif + +#endif /* GPIO_PARAMS_H */ +/** @} */ diff --git a/boards/stm32l0538-disco/include/periph_conf.h b/boards/stm32l0538-disco/include/periph_conf.h new file mode 100644 index 0000000000..3d314613d5 --- /dev/null +++ b/boards/stm32l0538-disco/include/periph_conf.h @@ -0,0 +1,150 @@ +/* + * Copyright (C) 2018 Inria + * + * This file is subject to the terms and conditions of the GNU Lesser General + * Public License v2.1. See the file LICENSE in the top level directory for more + * details. + */ + +/** + * @ingroup boards_stm32l0538-disco + * @{ + * + * @file + * @brief Peripheral MCU configuration for the STM32L0538-DISCO board + * + * @author Alexandre Abadie + */ + +#ifndef PERIPH_CONF_H +#define PERIPH_CONF_H + +#include "periph_cpu.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @name Clock system configuration + * @{ + */ +#define CLOCK_HSI (16000000U) /* internal oscillator */ +#define CLOCK_CORECLOCK (32000000U) /* desired core clock frequency */ +#define CLOCK_LSE (0) /* enable low speed external oscillator */ + +/* configuration of PLL prescaler and multiply values */ +/* CORECLOCK := HSI / CLOCK_PLL_DIV * CLOCK_PLL_MUL */ +#define CLOCK_PLL_DIV RCC_CFGR_PLLDIV2 +#define CLOCK_PLL_MUL RCC_CFGR_PLLMUL4 +/* configuration of peripheral bus clock prescalers */ +#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1 /* AHB clock -> 32MHz */ +#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* APB2 clock -> 32MHz */ +#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV1 /* APB1 clock -> 32MHz */ +/* configuration of flash access cycles */ +#define CLOCK_FLASH_LATENCY FLASH_ACR_LATENCY + +/* bus clocks for simplified peripheral initialization, UPDATE MANUALLY! */ +#define CLOCK_AHB (CLOCK_CORECLOCK / 1) +#define CLOCK_APB2 (CLOCK_CORECLOCK / 1) +#define CLOCK_APB1 (CLOCK_CORECLOCK / 1) +/** @} */ + +/** + * @name Timer configuration + * @{ + */ +static const timer_conf_t timer_config[] = { + { + .dev = TIM2, + .max = 0x0000ffff, + .rcc_mask = RCC_APB1ENR_TIM2EN, + .bus = APB1, + .irqn = TIM2_IRQn + } +}; + +#define TIMER_0_ISR isr_tim2 + +#define TIMER_NUMOF (sizeof(timer_config) / sizeof(timer_config[0])) +/** @} */ + +/** + * @name UART configuration + * @{ + */ +static const uart_conf_t uart_config[] = { + { + .dev = USART1, + .rcc_mask = RCC_APB2ENR_USART1EN, + .rx_pin = GPIO_PIN(PORT_A, 10), + .tx_pin = GPIO_PIN(PORT_A, 9), + .rx_af = GPIO_AF4, + .tx_af = GPIO_AF4, + .bus = APB2, + .irqn = USART1_IRQn, + .type = STM32_USART, + .clk_src = 0, /* Use APB clock */ + } +}; + +#define UART_0_ISR (isr_usart1) + +#define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0])) +/** @} */ + +/** + * @name SPI configuration + * + * @note The spi_divtable is auto-generated from + * `cpu/stm32_common/dist/spi_divtable/spi_divtable.c` + * @{ + */ +static const uint8_t spi_divtable[2][5] = { + { /* for APB1 @ 32000000Hz */ + 7, /* -> 125000Hz */ + 5, /* -> 500000Hz */ + 4, /* -> 1000000Hz */ + 2, /* -> 4000000Hz */ + 1 /* -> 8000000Hz */ + }, + { /* for APB2 @ 32000000Hz */ + 7, /* -> 125000Hz */ + 5, /* -> 500000Hz */ + 4, /* -> 1000000Hz */ + 2, /* -> 4000000Hz */ + 1 /* -> 8000000Hz */ + } +}; + +static const spi_conf_t spi_config[] = { + { + .dev = SPI1, + .mosi_pin = GPIO_PIN(PORT_B, 5), + .miso_pin = GPIO_PIN(PORT_B, 4), + .sclk_pin = GPIO_PIN(PORT_B, 3), + .cs_pin = GPIO_UNDEF, + .af = GPIO_AF0, + .rccmask = RCC_APB2ENR_SPI1EN, + .apbbus = APB2 + }, + { + .dev = SPI2, + .mosi_pin = GPIO_PIN(PORT_B, 15), + .miso_pin = GPIO_PIN(PORT_B, 14), + .sclk_pin = GPIO_PIN(PORT_B, 13), + .cs_pin = GPIO_PIN(PORT_B, 12), + .af = GPIO_AF0, + .rccmask = RCC_APB1ENR_SPI2EN, + .apbbus = APB1 + }, +}; + +#define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0])) +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif /* PERIPH_CONF_H */