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Merge pull request #7556 from haukepetersen/opt_sam0_uart
cpu/sam0: optimizations to the shared UART driver
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e5e70b2a28
@ -217,6 +217,60 @@ static inline int sercom_id(void *sercom)
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#endif
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}
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/**
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* @brief Enable peripheral clock for given SERCOM device
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*
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* @param[in] sercom SERCOM device
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*/
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static inline void sercom_clk_en(void *sercom)
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{
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#if defined(CPU_FAM_SAMD21)
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PM->APBCMASK.reg |= (PM_APBCMASK_SERCOM0 << sercom_id(sercom));
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#elif defined(CPU_FAM_SAML21)
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if (sercom_id(sercom) < 5) {
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MCLK->APBCMASK.reg |= (MCLK_APBCMASK_SERCOM0 << sercom_id(sercom));
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} else {
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MCLK->APBDMASK.reg |= (MCLK_APBDMASK_SERCOM5);
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}
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#endif
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}
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/**
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* @brief Disable peripheral clock for given SERCOM device
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*
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* @param[in] sercom SERCOM device
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*/
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static inline void sercom_clk_dis(void *sercom)
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{
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#if defined(CPU_FAM_SAMD21)
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PM->APBCMASK.reg &= ~(PM_APBCMASK_SERCOM0 << sercom_id(sercom));
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#elif defined(CPU_FAM_SAML21)
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if (sercom_id(sercom) < 5) {
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MCLK->APBCMASK.reg &= ~(MCLK_APBCMASK_SERCOM0 << sercom_id(sercom));
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} else {
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MCLK->APBDMASK.reg &= ~(MCLK_APBDMASK_SERCOM5);
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}
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#endif
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}
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/**
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* @brief Configure generator clock for given SERCOM device
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*
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* @param[in] sercom SERCOM device
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* @param[in] gclk Generator clock
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*/
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static inline void sercom_set_gen(void *sercom, uint32_t gclk)
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{
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#if defined(CPU_FAM_SAMD21)
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GCLK->CLKCTRL.reg = (GCLK_CLKCTRL_CLKEN | gclk |
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(SERCOM0_GCLK_ID_CORE + sercom_id(sercom)));
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while (GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY) {}
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#elif defined(CPU_FAM_SAML21)
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GCLK->PCHCTRL[SERCOM0_GCLK_ID_CORE + sercom_id(sercom)].reg =
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(GCLK_PCHCTRL_CHEN | gclk);
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#endif
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}
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/**
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* @brief ADC Channel Configuration
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*/
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@ -46,28 +46,11 @@ static uart_isr_ctx_t uart_ctx[UART_NUMOF];
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*
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* @return base register address
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*/
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static inline SercomUsart *_uart(uart_t dev)
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static inline SercomUsart *dev(uart_t dev)
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{
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return uart_config[dev].dev;
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}
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#ifdef CPU_FAM_SAML21
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static uint64_t _long_division(uint64_t n, uint64_t d);
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static uint8_t sercom_gclk_id[] =
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{
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SERCOM0_GCLK_ID_CORE,
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SERCOM1_GCLK_ID_CORE,
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SERCOM2_GCLK_ID_CORE,
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SERCOM3_GCLK_ID_CORE,
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SERCOM4_GCLK_ID_CORE,
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SERCOM5_GCLK_ID_CORE
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};
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#endif
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int uart_init(uart_t uart, uint32_t baudrate, uart_rx_cb_t rx_cb, void *arg)
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{
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if (uart >= UART_NUMOF) {
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@ -78,74 +61,48 @@ int uart_init(uart_t uart, uint32_t baudrate, uart_rx_cb_t rx_cb, void *arg)
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gpio_init(uart_config[uart].rx_pin, GPIO_IN);
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gpio_init_mux(uart_config[uart].rx_pin, uart_config[uart].mux);
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gpio_init(uart_config[uart].tx_pin, GPIO_OUT);
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gpio_set(uart_config[uart].tx_pin);
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gpio_init_mux(uart_config[uart].tx_pin, uart_config[uart].mux);
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#ifdef CPU_FAM_SAMD21
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/* calculate baudrate */
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uint32_t baud = ((((uint32_t)CLOCK_CORECLOCK * 10) / baudrate) / 16);
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/* enable sync and async clocks */
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uart_poweron(uart);
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/* enable peripheral clock */
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sercom_clk_en(dev(uart));
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/* reset the UART device */
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_uart(uart)->CTRLA.reg = SERCOM_USART_CTRLA_SWRST;
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while (_uart(uart)->SYNCBUSY.reg & SERCOM_USART_SYNCBUSY_SWRST) {}
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dev(uart)->CTRLA.reg = SERCOM_USART_CTRLA_SWRST;
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while (dev(uart)->SYNCBUSY.reg & SERCOM_USART_SYNCBUSY_SWRST) {}
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/* configure clock generator */
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sercom_set_gen(dev(uart), uart_config[uart].gclk_src);
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/* set asynchronous mode w/o parity, LSB first, TX and RX pad as specified
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* by the board in the periph_conf.h, x16 sampling and use internal clock */
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_uart(uart)->CTRLA.reg = (SERCOM_USART_CTRLA_DORD |
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dev(uart)->CTRLA.reg = (SERCOM_USART_CTRLA_DORD |
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SERCOM_USART_CTRLA_SAMPR(0x1) |
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SERCOM_USART_CTRLA_TXPO(uart_config[uart].tx_pad) |
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SERCOM_USART_CTRLA_RXPO(uart_config[uart].rx_pad) |
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SERCOM_USART_CTRLA_MODE_USART_INT_CLK |
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SERCOM_USART_CTRLA_MODE(0x1) |
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(uart_config[uart].runstdby ?
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SERCOM_USART_CTRLA_RUNSTDBY : 0));
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/* set baudrate */
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_uart(uart)->BAUD.FRAC.FP = (baud % 10);
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_uart(uart)->BAUD.FRAC.BAUD = (baud / 10);
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/* enable receiver and transmitter, use 1 stop bit */
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_uart(uart)->CTRLB.reg = (SERCOM_USART_CTRLB_RXEN | SERCOM_USART_CTRLB_TXEN);
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while (_uart(uart)->SYNCBUSY.reg & SERCOM_USART_SYNCBUSY_CTRLB) {}
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#elif CPU_FAM_SAML21
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/* Calculate the BAUD value */
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uint64_t temp1 = ((16 * ((uint64_t)baudrate)) << 32);
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uint64_t ratio = _long_division(temp1 , CLOCK_CORECLOCK);
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uint64_t scale = ((uint64_t)1 << 32) - ratio;
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uint64_t baud_calculated = (65536 * scale) >> 32;
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/* calculate and set baudrate */
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uint32_t baud = ((((uint32_t)CLOCK_CORECLOCK * 10) / baudrate) / 16);
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dev(uart)->BAUD.FRAC.FP = (baud % 10);
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dev(uart)->BAUD.FRAC.BAUD = (baud / 10);
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_uart(uart)->CTRLA.bit.ENABLE = 0; /* Disable to write, need to sync tho */
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while(_uart(uart)->SYNCBUSY.bit.ENABLE) {}
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/* set to LSB, asynchronous mode without parity, PAD0 Tx, PAD1 Rx,
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* 16x over-sampling, internal clk */
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_uart(uart)->CTRLA.reg = SERCOM_USART_CTRLA_DORD \
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| SERCOM_USART_CTRLA_FORM(0x0) \
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| SERCOM_USART_CTRLA_SAMPA(0x0) \
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| SERCOM_USART_CTRLA_TXPO(uart_config[uart].tx_pad) \
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| SERCOM_USART_CTRLA_RXPO(uart_config[uart].rx_pad) \
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| SERCOM_USART_CTRLA_SAMPR(0x0) \
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| SERCOM_USART_CTRLA_MODE(0x1) \
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| (uart_config[uart].runstdby ?
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SERCOM_USART_CTRLA_RUNSTDBY : 0);
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/* Set baud rate */
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_uart(uart)->BAUD.bit.BAUD = baud_calculated;
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/* enable receiver and transmitter, one stop bit*/
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_uart(uart)->CTRLB.reg = (SERCOM_USART_CTRLB_RXEN | SERCOM_USART_CTRLB_TXEN);
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while(_uart(uart)->SYNCBUSY.bit.CTRLB) {}
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uart_poweron(uart);
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#endif
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/* finally, enable the device */
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_uart(uart)->CTRLA.reg |= SERCOM_USART_CTRLA_ENABLE;
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/* register callbacks */
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/* enable transmitter, and configure 8N1 mode */
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dev(uart)->CTRLB.reg = (SERCOM_USART_CTRLB_TXEN);
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/* enable receiver and RX interrupt if configured */
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if (rx_cb) {
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uart_ctx[uart].rx_cb = rx_cb;
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uart_ctx[uart].arg = arg;
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/* configure interrupts and enable RX interrupt */
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NVIC_EnableIRQ(SERCOM0_IRQn + sercom_id(_uart(uart)));
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_uart(uart)->INTENSET.reg |= SERCOM_USART_INTENSET_RXC;
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NVIC_EnableIRQ(SERCOM0_IRQn + sercom_id(dev(uart)));
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dev(uart)->CTRLB.reg |= SERCOM_USART_CTRLB_RXEN;
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dev(uart)->INTENSET.reg |= SERCOM_USART_INTENSET_RXC;
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}
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while (dev(uart)->SYNCBUSY.reg & SERCOM_USART_SYNCBUSY_CTRLB) {}
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/* and finally enable the device */
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dev(uart)->CTRLA.reg |= SERCOM_USART_CTRLA_ENABLE;
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return UART_OK;
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}
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@ -153,85 +110,36 @@ int uart_init(uart_t uart, uint32_t baudrate, uart_rx_cb_t rx_cb, void *arg)
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void uart_write(uart_t uart, const uint8_t *data, size_t len)
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{
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for (size_t i = 0; i < len; i++) {
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while (!(_uart(uart)->INTFLAG.reg & SERCOM_USART_INTFLAG_DRE)) {}
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_uart(uart)->DATA.reg = data[i];
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while (_uart(uart)->INTFLAG.reg & SERCOM_USART_INTFLAG_TXC) {}
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while (!(dev(uart)->INTFLAG.reg & SERCOM_USART_INTFLAG_DRE)) {}
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dev(uart)->DATA.reg = data[i];
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while (dev(uart)->INTFLAG.reg & SERCOM_USART_INTFLAG_TXC) {}
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}
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}
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void uart_poweron(uart_t uart)
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{
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#ifdef CPU_FAM_SAMD21
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PM->APBCMASK.reg |= (PM_APBCMASK_SERCOM0 << sercom_id(_uart(uart)));
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GCLK->CLKCTRL.reg = (GCLK_CLKCTRL_CLKEN |
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GCLK_CLKCTRL_GEN(uart_config[uart].gclk_src) |
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(SERCOM0_GCLK_ID_CORE + sercom_id(_uart(uart))) <<
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GCLK_CLKCTRL_ID_Pos);
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while (GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY) {}
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#elif CPU_FAM_SAML21
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/* Enable the peripheral channel */
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GCLK->PCHCTRL[sercom_gclk_id[sercom_id(_uart(uart))]].reg |=
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GCLK_PCHCTRL_CHEN | GCLK_PCHCTRL_GEN(uart_config[uart].gclk_src);
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while (!(GCLK->PCHCTRL[sercom_gclk_id[sercom_id(_uart(uart))]].reg &
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GCLK_PCHCTRL_CHEN)) {}
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if(sercom_gclk_id[sercom_id(_uart(uart))] < 5) {
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MCLK->APBCMASK.reg |= MCLK_APBCMASK_SERCOM0 << sercom_id(_uart(uart));
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}
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else {
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MCLK->APBDMASK.reg |= MCLK_APBDMASK_SERCOM5;
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}
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while (_uart(uart)->SYNCBUSY.reg) {}
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#endif
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/* finally, enable the device */
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_uart(uart)->CTRLA.reg |= SERCOM_USART_CTRLA_ENABLE;
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sercom_clk_en(dev(uart));
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dev(uart)->CTRLA.reg |= SERCOM_USART_CTRLA_ENABLE;
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}
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void uart_poweroff(uart_t uart)
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{
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#ifdef CPU_FAM_SAMD21
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PM->APBCMASK.reg &= ~(PM_APBCMASK_SERCOM0 << sercom_id(_uart(uart)));
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GCLK->CLKCTRL.reg = ((SERCOM0_GCLK_ID_CORE + sercom_id(_uart(uart))) <<
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GCLK_CLKCTRL_ID_Pos);
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while (GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY) {}
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#elif CPU_FAM_SAML21
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/* Enable the peripheral channel */
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GCLK->PCHCTRL[sercom_gclk_id[sercom_id(_uart(uart))]].reg &= ~GCLK_PCHCTRL_CHEN;
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if(sercom_gclk_id[sercom_id(_uart(uart))] < 5) {
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MCLK->APBCMASK.reg &= ~(MCLK_APBCMASK_SERCOM0 << sercom_id(_uart(uart)));
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}
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else {
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MCLK->APBDMASK.reg &= ~MCLK_APBDMASK_SERCOM5;
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}
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while (_uart(uart)->SYNCBUSY.reg) {}
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#endif
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dev(uart)->CTRLA.reg &= ~(SERCOM_USART_CTRLA_ENABLE);
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sercom_clk_dis(dev(uart));
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}
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static inline void irq_handler(uint8_t uartnum)
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static inline void irq_handler(unsigned uartnum)
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{
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#ifdef CPU_FAM_SAMD21
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if (_uart(uartnum)->INTFLAG.reg & SERCOM_USART_INTFLAG_RXC) {
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if (dev(uartnum)->INTFLAG.reg & SERCOM_USART_INTFLAG_RXC) {
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/* interrupt flag is cleared by reading the data register */
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uart_ctx[uartnum].rx_cb(uart_ctx[uartnum].arg,
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(uint8_t)(_uart(uartnum)->DATA.reg));
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(uint8_t)(dev(uartnum)->DATA.reg));
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}
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else if (_uart(uartnum)->INTFLAG.reg & SERCOM_USART_INTFLAG_ERROR) {
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else if (dev(uartnum)->INTFLAG.reg & SERCOM_USART_INTFLAG_ERROR) {
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/* clear error flag */
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_uart(uartnum)->INTFLAG.reg = SERCOM_USART_INTFLAG_ERROR;
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dev(uartnum)->INTFLAG.reg = SERCOM_USART_INTFLAG_ERROR;
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}
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#elif CPU_FAM_SAML21
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if (_uart(uartnum)->INTFLAG.bit.RXC) {
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/* cleared by reading DATA regiser */
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uint8_t data = (uint8_t)_uart(uartnum)->DATA.reg;
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uart_ctx[uartnum].rx_cb(uart_ctx[uartnum].arg, data);
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}
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else if (_uart(uartnum)->INTFLAG.bit.ERROR) {
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/* clear error flag */
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_uart(uartnum)->INTFLAG.reg |= SERCOM_USART_INTFLAG_ERROR;
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}
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#endif
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cortexm_isr_end();
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}
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@ -277,28 +185,4 @@ void UART_5_ISR(void)
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}
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#endif
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#ifdef CPU_FAM_SAML21
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static uint64_t _long_division(uint64_t n, uint64_t d)
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{
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int32_t i;
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uint64_t q = 0, r = 0, bit_shift;
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for (i = 63; i >= 0; i--) {
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bit_shift = (uint64_t)1 << i;
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r = r << 1;
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if (n & bit_shift) {
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r |= 0x01;
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}
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if (r >= d) {
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r = r - d;
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q |= bit_shift;
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}
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}
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return q;
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}
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#endif
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#endif /* UART_NUMOF */
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