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Merge #19076
19076: boards/hip-badge: add HiP Badge board definition r=maribu a=benpicco Co-authored-by: Benjamin Valentin <benpicco@beuth-hochschule.de>
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21
boards/hip-badge/Kconfig
Normal file
21
boards/hip-badge/Kconfig
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@ -0,0 +1,21 @@
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# Copyright (c) 2023 Benjamin Valentin
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#
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# This file is subject to the terms and conditions of the GNU Lesser
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# General Public License v2.1. See the file LICENSE in the top level
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# directory for more details.
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config BOARD
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default "hip-badge" if BOARD_HIP_BADGE
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config BOARD_HIP_BADGE
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bool
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default y
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select BOARD_COMMON_ESP32C3
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select CPU_MODEL_ESP32C3
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select HAS_ESP_JTAG
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select HAS_PERIPH_I2C
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select HAVE_SAUL_GPIO
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select HAVE_SGP30
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source "$(RIOTBOARD)/common/esp32c3/Kconfig"
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5
boards/hip-badge/Makefile
Normal file
5
boards/hip-badge/Makefile
Normal file
@ -0,0 +1,5 @@
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MODULE = board
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DIRS = $(RIOTBOARD)/common/esp32c3
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include $(RIOTBASE)/Makefile.base
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9
boards/hip-badge/Makefile.dep
Normal file
9
boards/hip-badge/Makefile.dep
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@ -0,0 +1,9 @@
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ifeq (,$(filter stdio_% slipdev_stdio,$(USEMODULE)))
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USEMODULE += stdio_usb_serial_jtag
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endif
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ifneq (,$(filter saul_default,$(USEMODULE)))
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USEMODULE += sgp30
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endif
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include $(RIOTBOARD)/common/esp32c3/Makefile.dep
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10
boards/hip-badge/Makefile.features
Normal file
10
boards/hip-badge/Makefile.features
Normal file
@ -0,0 +1,10 @@
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CPU_MODEL = esp32c3
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# common board and CPU features
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include $(RIOTBOARD)/common/esp32c3/Makefile.features
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# additional features provided by the board
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FEATURES_PROVIDED += periph_i2c
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# unique features provided by the board
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FEATURES_PROVIDED += esp_jtag
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3
boards/hip-badge/Makefile.include
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3
boards/hip-badge/Makefile.include
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@ -0,0 +1,3 @@
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PORT_LINUX ?= /dev/ttyACM0
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include $(RIOTBOARD)/common/esp32c3/Makefile.include
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62
boards/hip-badge/doc.txt
Normal file
62
boards/hip-badge/doc.txt
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@ -0,0 +1,62 @@
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/*
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* Copyright (C) 2023 Benjamin Valentin
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @defgroup boards_hip_badge HiP Badge
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* @ingroup boards_esp32c3
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* @brief Support for the Hacking in Parallel Badge
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* @author Benjamin Valentin <benjamin.valentin@ml-pa.com>
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*/
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The HiP Badge is a board that was given to participants of the 2022 *Hacking in Parallel* event.
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# Features
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- ESP32-C3FH4AZ SoC
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- I2C via SAO headers
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- UART via pin headers
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- 16 WS2812B LEDs
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- USB-C Serial/JTAG
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- 3 User button / 1 Reset button
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- ST25DV04K NFC/I2C EEPROM (TODO: driver)
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# Flashing the device
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The device can be programmed using the USB-C Serial/JTAG feature.
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Just plug in a cable to your computer and flash the device with
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make BOARD=hip-badge flash
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This should automatically reset the ESP32C3 into bootloader mode and start the download process.
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If for some reason this gets stuck or the badge does not register as a /dev/ttyACMx device, you
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can manually force it into bootloader mode by pressing the reset button (SW3/blue) while holding
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the BOOT button (SW4).
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When doing this, the device will still be in bootloader mode after flashing, you have to press
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the reset button (SW3/blue) again to start your application.
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There is currently still a bug in the USB Serial stdio implementation: After flashing or a reboot,
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there is no output. Do a manual reset (press the reset button) to restore output.
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# Bugs
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The event (and badge) were organized on short notice (6 Weeks), so there are some hardware issues:
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- No WiFi/BLE antenna. There is a pad on the back of the PCB where a socket was supposed to be, but
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nothing is connected. You can try solder something onto it yourself, but the trace is already long
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and winded.
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BLE works with the existing trace alone (on short range), WiFi/ESP Now does not.
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- IR transceiver broken. Can be fixed with a steady hand?
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- SGP30 air quality sensor is only populated on some boards (red case)
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- MAX17048 fuel gauge not populated
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# Resources
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- [Badge Clinic](https://wiki.hip-berlin.de/index.php?title=Badge_Clinic)
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- [Design files](https://gitlab.com/tidklaas/hip-badge/)
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1
boards/hip-badge/hip-badge.config
Normal file
1
boards/hip-badge/hip-badge.config
Normal file
@ -0,0 +1 @@
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CONFIG_MODULE_STDIO_USB_SERIAL_JTAG=y
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117
boards/hip-badge/include/board.h
Normal file
117
boards/hip-badge/include/board.h
Normal file
@ -0,0 +1,117 @@
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/*
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* Copyright (C) 2023 Benjamin Valentin
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup boards_hip_badge
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* @brief Board definitions for the HiP Badge
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* @{
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*
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* @file
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* @author Benjamin Valentin <benjamin.valentin@ml-pa.com>
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*/
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#ifndef BOARD_H
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#define BOARD_H
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#include <stdint.h>
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/**
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* @name Button pin definitions
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* @{
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*/
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/**
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* @brief Tact A GPIO pin definition
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*/
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#define BTN0_PIN GPIO2
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/**
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* @brief button GPIO mode definition
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*
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* Since the GPIO of the button is pulled up with an external resistor, the
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* mode for the GPIO pin has to be GPIO_IN.
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*/
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#define BTN0_MODE GPIO_IN
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/**
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* @brief Default interrupt flank definition for the button GPIO
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*/
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#ifndef BTN0_INT_FLANK
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#define BTN0_INT_FLANK GPIO_FALLING
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#endif
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/**
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* @brief Tact B GPIO pin definition
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*/
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#define BTN1_PIN GPIO8
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/**
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* @brief Default button GPIO mode definition
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*
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* Since the GPIO of the button is pulled up with an external resistor, the
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* mode for the GPIO pin has to be GPIO_IN.
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*/
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#define BTN1_MODE GPIO_IN
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/**
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* @brief Default interrupt flank definition for the button GPIO
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*/
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#ifndef BTN1_INT_FLANK
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#define BTN1_INT_FLANK GPIO_FALLING
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#endif
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/**
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* @brief BOOT button GPIO pin definition
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*
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* The HiP-Badge has a BOOT button connected to GPIO9, which can be
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* used as button during normal operation. Since the GPIO9 pin is pulled up,
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* the button signal is inverted, i.e., pressing the button will give a
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* low signal.
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*/
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#define BTN2_PIN GPIO9
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/**
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* @brief Default button GPIO mode definition
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*/
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#define BTN2_MODE GPIO_IN_PU
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/**
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* @brief Default interrupt flank definition for the button GPIO
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*/
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#ifndef BTN2_INT_FLANK
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#define BTN2_INT_FLANK GPIO_FALLING
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#endif
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/** @} */
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/**
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* @brief WS281x LEDs are connected to GPIO10
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*/
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#ifndef WS281X_PARAM_PIN
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#define WS281X_PARAM_PIN GPIO10
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#endif
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/**
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* @brief There are 16 WS281x LEDs
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*/
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#ifndef WS281X_PARAM_NUMOF
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#define WS281X_PARAM_NUMOF 16
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#endif
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/* include common board definitions as last step */
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#include "board_common.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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#ifdef __cplusplus
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} /* end extern "C" */
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#endif
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#endif /* BOARD_H */
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/** @} */
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57
boards/hip-badge/include/gpio_params.h
Normal file
57
boards/hip-badge/include/gpio_params.h
Normal file
@ -0,0 +1,57 @@
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/*
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* Copyright (C) 2023 Benjamin Valentin
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup boards_hip_badge
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* @brief Board specific configuration of direct mapped GPIOs
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* @file
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* @author Benjamin Valentin <benjamin.valentin@ml-pa.com>
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* @{
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*/
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#ifndef GPIO_PARAMS_H
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#define GPIO_PARAMS_H
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#include "board.h"
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#include "saul/periph.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @brief LED and Button configuration
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*/
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static const saul_gpio_params_t saul_gpio_params[] =
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{
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{
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.name = "SW1",
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.pin = BTN0_PIN,
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.mode = BTN0_MODE,
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.flags = SAUL_GPIO_INVERTED
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},
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{
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.name = "SW2",
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.pin = BTN1_PIN,
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.mode = BTN1_MODE,
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.flags = SAUL_GPIO_INVERTED
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},
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{
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.name = "Boot",
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.pin = BTN2_PIN,
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.mode = BTN2_MODE,
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.flags = SAUL_GPIO_INVERTED
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},
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};
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#ifdef __cplusplus
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}
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#endif
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#endif /* GPIO_PARAMS_H */
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/** @} */
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74
boards/hip-badge/include/periph_conf.h
Normal file
74
boards/hip-badge/include/periph_conf.h
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@ -0,0 +1,74 @@
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/*
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* Copyright (C) 2023 Benjamin Valentin
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup boards_hip_badge
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* @brief Peripheral configurations for the HiP Badge
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* @{
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*
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* @file
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* @author Benjamin Valentin <benjamin.valentin@ml-pa.com>
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*/
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#ifndef PERIPH_CONF_H
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#define PERIPH_CONF_H
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#include <stdint.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @name I2C configuration
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*
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* One I2C interface I2C_DEV(0) is defined and available via the SAO headers.
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*
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* The GPIOs listed in the configuration are only initialized as I2C signals
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* when module `periph_i2c` is used. Otherwise they are not allocated and
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* can be used for other purposes.
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*
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* @{
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*/
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#ifndef I2C0_SPEED
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#define I2C0_SPEED I2C_SPEED_FAST /**< I2C bus speed of I2C_DEV(0) */
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#endif
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#ifndef I2C0_SCL
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#define I2C0_SCL GPIO6 /**< SCL signal of I2C_DEV(0) */
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#endif
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#ifndef I2C0_SDA
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#define I2C0_SDA GPIO5 /**< SDA signal of I2C_DEV(0) */
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#endif
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/** @} */
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/**
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* @name UART configuration
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*
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* ESP32-C3 provides 2 UART interfaces at maximum:
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*
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* UART_DEV(0) uses fixed standard configuration.<br>
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* UART_DEV(1) is used for IrDA (untested).<br>
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*
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* @{
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*/
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#define UART0_TXD GPIO21 /**< direct I/O pin for UART_DEV(0) TxD, can't be changed */
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#define UART0_RXD GPIO20 /**< direct I/O pin for UART_DEV(0) RxD, can't be changed */
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#define UART1_TXD GPIO7 /**< IrDA TX - Bad Choice? */
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#define UART1_RXD GPIO3 /**< IrDA RX - Bad Choice? */
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/** @} */
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#ifdef __cplusplus
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} /* end extern "C" */
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#endif
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/* include common peripheral definitions as last step */
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#include "periph_conf_common.h"
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#endif /* PERIPH_CONF_H */
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/** @} */
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@ -25,6 +25,10 @@ ifneq (, $(filter esp_freertos, $(USEMODULE)))
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DIRS += freertos
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endif
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ifneq (, $(filter stdio_usb_serial_jtag, $(USEMODULE)))
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DIRS += stdio_usb_serial_jtag
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endif
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ifneq (,$(filter esp_wifi% esp_eth, $(USEMODULE)))
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SRC += esp_ztimer.c
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endif
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@ -166,6 +166,17 @@ ifneq (,$(filter shell,$(USEMODULE)))
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USEMODULE += ps
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endif
|
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ifneq (,$(filter stdio_usb_serial_jtag, $(USEMODULE)))
|
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USEMODULE += tsrb
|
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ifneq (,$(filter stdin,$(USEMODULE)))
|
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USEMODULE += stdio_usb_serial_jtag_rx
|
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endif
|
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endif
|
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ifneq (,$(filter stdio_usb_serial_jtag_rx, $(USEMODULE)))
|
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USEMODULE += isrpipe
|
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USEMODULE += stdio_available
|
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endif
|
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ifneq (,$(filter tinyusb_portable_espressif,$(USEMODULE)))
|
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USEMODULE += esp_idf_usb
|
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endif
|
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|
||||
@ -50,6 +50,7 @@ PSEUDOMODULES += esp_rtc_timer_32k
|
||||
PSEUDOMODULES += esp_spi_ram
|
||||
PSEUDOMODULES += esp_spi_oct
|
||||
PSEUDOMODULES += esp_wifi_enterprise
|
||||
PSEUDOMODULES += stdio_usb_serial_jtag_rx
|
||||
|
||||
INCLUDES += -I$(RIOTCPU)/$(CPU)/esp-idf/include
|
||||
INCLUDES += -I$(RIOTCPU)/$(CPU)/esp-idf/include/log
|
||||
|
||||
@ -36,20 +36,21 @@ extern "C" {
|
||||
*
|
||||
* @{
|
||||
*/
|
||||
#define CPU_INUM_GPIO 2 /**< Level interrupt with low priority 1 */
|
||||
#define CPU_INUM_CAN 3 /**< Level interrupt with low priority 1 */
|
||||
#define CPU_INUM_UART 4 /**< Level interrupt with low priority 1 */
|
||||
#define CPU_INUM_USB 8 /**< Level interrupt with low priority 1 */
|
||||
#define CPU_INUM_RTT 9 /**< Level interrupt with low priority 1 */
|
||||
#define CPU_INUM_I2C 12 /**< Level interrupt with low priority 1 */
|
||||
#define CPU_INUM_WDT 13 /**< Level interrupt with low priority 1 */
|
||||
#define CPU_INUM_SOFTWARE 17 /**< Level interrupt with low priority 1 */
|
||||
#define CPU_INUM_ETH 18 /**< Level interrupt with low priority 1 */
|
||||
#define CPU_INUM_TIMER 19 /**< Level interrupt with medium priority 2 */
|
||||
#define CPU_INUM_FRC2 20 /**< Level interrupt with medium priority 2 */
|
||||
#define CPU_INUM_SYSTIMER 20 /**< Level interrupt with medium priority 2 */
|
||||
#define CPU_INUM_BLE 21 /**< Level interrupt with medium priority 2 */
|
||||
#define CPU_INUM_CACHEERR 25 /**< Level interrupt with high priority 4 */
|
||||
#define CPU_INUM_GPIO 2 /**< Level interrupt with low priority 1 */
|
||||
#define CPU_INUM_CAN 3 /**< Level interrupt with low priority 1 */
|
||||
#define CPU_INUM_UART 4 /**< Level interrupt with low priority 1 */
|
||||
#define CPU_INUM_USB 8 /**< Level interrupt with low priority 1 */
|
||||
#define CPU_INUM_RTT 9 /**< Level interrupt with low priority 1 */
|
||||
#define CPU_INUM_SERIAL_JTAG 10 /**< Level interrupt with low priority 1 */
|
||||
#define CPU_INUM_I2C 12 /**< Level interrupt with low priority 1 */
|
||||
#define CPU_INUM_WDT 13 /**< Level interrupt with low priority 1 */
|
||||
#define CPU_INUM_SOFTWARE 17 /**< Level interrupt with low priority 1 */
|
||||
#define CPU_INUM_ETH 18 /**< Level interrupt with low priority 1 */
|
||||
#define CPU_INUM_TIMER 19 /**< Level interrupt with medium priority 2 */
|
||||
#define CPU_INUM_FRC2 20 /**< Level interrupt with medium priority 2 */
|
||||
#define CPU_INUM_SYSTIMER 20 /**< Level interrupt with medium priority 2 */
|
||||
#define CPU_INUM_BLE 21 /**< Level interrupt with medium priority 2 */
|
||||
#define CPU_INUM_CACHEERR 25 /**< Level interrupt with high priority 4 */
|
||||
/** @} */
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||||
|
||||
/**
|
||||
|
||||
@ -83,6 +83,9 @@ static const struct intr_handle_data_t _irq_data_table[] = {
|
||||
#if defined(CPU_FAM_ESP32S2) || defined(CPU_FAM_ESP32S3)
|
||||
{ ETS_USB_INTR_SOURCE, CPU_INUM_USB, 1 },
|
||||
#endif
|
||||
#if defined(ETS_USB_SERIAL_JTAG_INTR_SOURCE)
|
||||
{ ETS_USB_SERIAL_JTAG_INTR_SOURCE, CPU_INUM_SERIAL_JTAG, 1 },
|
||||
#endif
|
||||
};
|
||||
|
||||
#define IRQ_DATA_TABLE_SIZE ARRAY_SIZE(_irq_data_table)
|
||||
|
||||
1
cpu/esp32/stdio_usb_serial_jtag/Makefile
Normal file
1
cpu/esp32/stdio_usb_serial_jtag/Makefile
Normal file
@ -0,0 +1 @@
|
||||
include $(RIOTBASE)/Makefile.base
|
||||
126
cpu/esp32/stdio_usb_serial_jtag/usb_serial_jtag.c
Normal file
126
cpu/esp32/stdio_usb_serial_jtag/usb_serial_jtag.c
Normal file
@ -0,0 +1,126 @@
|
||||
/*
|
||||
* Copyright (C) 2023 Benjamin Valentin
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU Lesser
|
||||
* General Public License v2.1. See the file LICENSE in the top level
|
||||
* directory for more details.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup cpu_esp32_usb_serial_jtag ESP32 USB Serial/JTAG interface
|
||||
* @ingroup cpu_esp32
|
||||
* @{
|
||||
*
|
||||
* @file
|
||||
* @brief stdio via USB Serial JTAG debug interface
|
||||
*
|
||||
* @author Benjamin Valentin <benjamin.valentin@ml-pa.com>
|
||||
*/
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stddef.h>
|
||||
#include <errno.h>
|
||||
#include <sys/types.h>
|
||||
|
||||
#include "isrpipe.h"
|
||||
#include "tsrb.h"
|
||||
|
||||
#include "irq_arch.h"
|
||||
#include "esp_attr.h"
|
||||
#include "hal/interrupt_controller_types.h"
|
||||
#include "hal/interrupt_controller_ll.h"
|
||||
#include "hal/usb_serial_jtag_ll.h"
|
||||
#include "soc/periph_defs.h"
|
||||
#include "rom/ets_sys.h"
|
||||
|
||||
static uint8_t _rx_buf_mem[USB_SERIAL_JTAG_PACKET_SZ_BYTES];
|
||||
static isrpipe_t stdio_serial_isrpipe = ISRPIPE_INIT(_rx_buf_mem);
|
||||
|
||||
static tsrb_t serial_tx_rb;
|
||||
static uint8_t serial_tx_rb_buf[USB_SERIAL_JTAG_PACKET_SZ_BYTES];
|
||||
|
||||
#define IRQ_MASK (USB_SERIAL_JTAG_INTR_SERIAL_IN_EMPTY | \
|
||||
(IS_USED(MODULE_STDIO_USB_SERIAL_JTAG_RX) * USB_SERIAL_JTAG_INTR_SERIAL_OUT_RECV_PKT))
|
||||
|
||||
ssize_t stdio_write(const void *buffer, size_t len)
|
||||
{
|
||||
tsrb_add(&serial_tx_rb, buffer, len);
|
||||
USB_SERIAL_JTAG.int_ena.val = IRQ_MASK;
|
||||
|
||||
return len;
|
||||
}
|
||||
|
||||
ssize_t stdio_read(void* buffer, size_t count)
|
||||
{
|
||||
if (IS_USED(MODULE_STDIO_USB_SERIAL_JTAG_RX)) {
|
||||
return (ssize_t)isrpipe_read(&stdio_serial_isrpipe, buffer, count);
|
||||
}
|
||||
|
||||
return -ENOTSUP;
|
||||
}
|
||||
|
||||
int stdio_available(void)
|
||||
{
|
||||
if (IS_USED(MODULE_STDIO_AVAILABLE)) {
|
||||
return tsrb_avail(&stdio_serial_isrpipe.tsrb);
|
||||
}
|
||||
|
||||
return -ENOTSUP;
|
||||
}
|
||||
|
||||
IRAM_ATTR
|
||||
static void _serial_intr_handler(void *arg)
|
||||
{
|
||||
(void)arg;
|
||||
|
||||
irq_isr_enter();
|
||||
|
||||
uint32_t mask = usb_serial_jtag_ll_get_intsts_mask();
|
||||
|
||||
/* read data if available */
|
||||
while (IS_USED(MODULE_STDIO_USB_SERIAL_JTAG_RX) &&
|
||||
usb_serial_jtag_ll_rxfifo_data_available()) {
|
||||
isrpipe_write_one(&stdio_serial_isrpipe, USB_SERIAL_JTAG.ep1.rdwr_byte);
|
||||
}
|
||||
|
||||
/* write data if there is a free stop */
|
||||
if (mask & USB_SERIAL_JTAG_INTR_SERIAL_IN_EMPTY) {
|
||||
|
||||
while (usb_serial_jtag_ll_txfifo_writable()) {
|
||||
int c = tsrb_get_one(&serial_tx_rb);
|
||||
if (c < 0) {
|
||||
/* no more data to send - disable interrupt */
|
||||
USB_SERIAL_JTAG.int_ena.val = IRQ_MASK & ~USB_SERIAL_JTAG_INTR_SERIAL_IN_EMPTY;
|
||||
break;
|
||||
}
|
||||
USB_SERIAL_JTAG.ep1.rdwr_byte = c;
|
||||
}
|
||||
usb_serial_jtag_ll_txfifo_flush();
|
||||
}
|
||||
|
||||
/* clear all interrupt flags */
|
||||
usb_serial_jtag_ll_clr_intsts_mask(mask);
|
||||
|
||||
irq_isr_exit();
|
||||
}
|
||||
|
||||
void stdio_init(void)
|
||||
{
|
||||
tsrb_init(&serial_tx_rb, serial_tx_rb_buf, sizeof(serial_tx_rb_buf));
|
||||
|
||||
/* enable RX interrupt */
|
||||
if (IS_USED(MODULE_STDIO_USB_SERIAL_JTAG_RX)) {
|
||||
USB_SERIAL_JTAG.int_ena.val = USB_SERIAL_JTAG_INTR_SERIAL_OUT_RECV_PKT;
|
||||
}
|
||||
|
||||
/* clear all interrupt flags */
|
||||
usb_serial_jtag_ll_clr_intsts_mask(USB_SERIAL_JTAG_LL_INTR_MASK);
|
||||
|
||||
/* route all UART interrupt sources to same the CPU interrupt */
|
||||
intr_matrix_set(PRO_CPU_NUM, ETS_USB_SERIAL_JTAG_INTR_SOURCE, CPU_INUM_SERIAL_JTAG);
|
||||
|
||||
/* we have to enable therefore the CPU interrupt here */
|
||||
intr_cntrl_ll_set_int_handler(CPU_INUM_SERIAL_JTAG, _serial_intr_handler, NULL);
|
||||
intr_cntrl_ll_enable_interrupts(BIT(CPU_INUM_SERIAL_JTAG));
|
||||
}
|
||||
/**@}*/
|
||||
@ -10,6 +10,7 @@ STDIO_MODULES = \
|
||||
stdio_uart \
|
||||
stdio_telnet \
|
||||
stdio_tinyusb_cdc_acm \
|
||||
stdio_usb_serial_jtag \
|
||||
#
|
||||
|
||||
# select stdio_uart if no other stdio module is slected
|
||||
|
||||
@ -49,6 +49,12 @@ config MODULE_STDIO_ETHOS
|
||||
select MODULE_ETHOS_STDIO
|
||||
select USE_STDOUT_BUFFERED
|
||||
|
||||
config MODULE_STDIO_USB_SERIAL_JTAG
|
||||
bool "STDIO via ESP32 Debug USB Serial/JTAG interface"
|
||||
depends on TEST_KCONFIG
|
||||
depends on CPU_FAM_ESP32C3 || CPU_FAM_ESP32S3
|
||||
select MODULE_TSRB
|
||||
|
||||
endchoice
|
||||
|
||||
config MODULE_STDIN
|
||||
@ -63,6 +69,15 @@ config MODULE_STDIO_UART_RX
|
||||
help
|
||||
Reception when using UART-based STDIO needs to be enabled.
|
||||
|
||||
config MODULE_STDIO_USB_SERIAL_JTAG_RX
|
||||
bool
|
||||
depends on MODULE_STDIO_USB_SERIAL_JTAG
|
||||
select MODULE_ISRPIPE
|
||||
select MODULE_STDIO_AVAILABLE
|
||||
default y if MODULE_STDIN
|
||||
help
|
||||
Reception when using ESP32 USB Serial/JTAG STDIO needs to be enabled.
|
||||
|
||||
config MODULE_STDIO_AVAILABLE
|
||||
bool
|
||||
help
|
||||
|
||||
Loading…
Reference in New Issue
Block a user