mirror of
https://github.com/RIOT-OS/RIOT.git
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boards: p-nucleo-wb55 initial support
This commit is contained in:
Francisco Molina
parent
c6e0e7adcb
commit
e220483adc
3
boards/common/stm32/dist/stm32wb.cfg
vendored
Normal file
3
boards/common/stm32/dist/stm32wb.cfg
vendored
Normal file
@ -0,0 +1,3 @@
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source [find target/stm32wbx.cfg]
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reset_config srst_only
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$_TARGETNAME configure -rtos auto
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@ -47,7 +47,7 @@ static const i2c_conf_t i2c_config[] = {
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.rcc_mask = RCC_APB1ENR_I2C1EN,
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.clk = CLOCK_APB1,
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.irqn = I2C1_EV_IRQn,
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#elif CPU_FAM_STM32L4
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#elif CPU_FAM_STM32L4 || CPU_FAM_STM32WB
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.rcc_mask = RCC_APB1ENR1_I2C1EN,
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.irqn = I2C1_ER_IRQn,
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#elif CPU_FAM_STM32F7
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@ -65,7 +65,7 @@ static const i2c_conf_t i2c_config[] = {
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#if CPU_FAM_STM32F4 || CPU_FAM_STM32F2
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#define I2C_0_ISR isr_i2c1_ev
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#elif CPU_FAM_STM32L4 || CPU_FAM_STM32F7
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#elif CPU_FAM_STM32L4 || CPU_FAM_STM32F7 || CPU_FAM_STM32WB
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#define I2C_0_ISR isr_i2c1_er
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#elif CPU_FAM_STM32F0 || CPU_FAM_STM32L0
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#define I2C_0_ISR isr_i2c1
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@ -37,7 +37,7 @@ static const timer_conf_t timer_config[] = {
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#else
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.max = 0xffffffff,
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#endif
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#if CPU_FAM_STM32L4
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#if defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32WB)
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.rcc_mask = RCC_APB1ENR1_TIM2EN,
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#else
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.rcc_mask = RCC_APB1ENR_TIM2EN,
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4
boards/p-nucleo-wb55/Makefile
Normal file
4
boards/p-nucleo-wb55/Makefile
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@ -0,0 +1,4 @@
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MODULE = board
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DIRS = $(RIOTBOARD)/common/nucleo
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include $(RIOTBASE)/Makefile.base
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3
boards/p-nucleo-wb55/Makefile.dep
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3
boards/p-nucleo-wb55/Makefile.dep
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@ -0,0 +1,3 @@
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FEATURES_REQUIRED += periph_lpuart
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include $(RIOTBOARD)/common/nucleo/Makefile.dep
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16
boards/p-nucleo-wb55/Makefile.features
Normal file
16
boards/p-nucleo-wb55/Makefile.features
Normal file
@ -0,0 +1,16 @@
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## the cpu to build for
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CPU = stm32wb
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CPU_MODEL = stm32wb55rg
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# Put defined MCU peripherals here (in alphabetical order)
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FEATURES_PROVIDED += periph_i2c
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FEATURES_PROVIDED += periph_lpuart
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FEATURES_PROVIDED += periph_rtc
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FEATURES_PROVIDED += periph_rtt
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FEATURES_PROVIDED += periph_spi
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FEATURES_PROVIDED += periph_timer
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FEATURES_PROVIDED += periph_uart
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# Put other features for this board (in alphabetical order)
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FEATURES_PROVIDED += arduino
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FEATURES_PROVIDED += riotboot
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14
boards/p-nucleo-wb55/Makefile.include
Normal file
14
boards/p-nucleo-wb55/Makefile.include
Normal file
@ -0,0 +1,14 @@
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# CPU2 defines a restricted memory region. This is not available for
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# CPU1 linking or general access, for now we define it by its default
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# value.
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CPU2_ROM_LEN = 216K
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# CPU2 can define restricted SRAM within SRAM2a and SRAM2b. These subregions
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# will generate busfaults if accessed by CPU1. For now we will assume that both
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# SRAM2a regions are completely dedicated to CPU2.
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CPU2_RAM_LEN = 64K
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OPENOCD_RESET_USE_CONNECT_ASSERT_SRST ?= 1
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# include shared global Nucleo Makefile
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include $(RIOTBOARD)/common/nucleo/Makefile.include
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110
boards/p-nucleo-wb55/doc.txt
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110
boards/p-nucleo-wb55/doc.txt
Normal file
@ -0,0 +1,110 @@
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/**
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@defgroup boards_p-nucleo-wb55 STM32 p-nucleo-wb55
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@ingroup boards_common_nucleo
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@brief Support for the STM32 p-nucleo-wb55
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Hardware
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========
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MCU
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---
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| MCU | STM32WB55RG |
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|:---------- |:------------------------------- |
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| Family | ARM Cortex-M4 |
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| Vendor | ST Microelectronics |
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| RAM | 256KB |
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| Flash | 512KB |
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| Frequency | 64MHz |
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| FPU | yes |
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| Timers | 8 (3x 16-bit, 1x 32-bit [TIM5]) |
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| LPTimers | 2x 16-bit |
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| ADCs | 1x 19-channel 12-bit |
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| UARTs | 1 |
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| LUARTs | 1 |
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| SPIs | 1 |
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| I2Cs | 2 |
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| RTC | 1 |
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| Vcc | 1.65V - 3.6V |
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| Datasheet | [Datasheet](https://www.st.com/resource/en/datasheet/stm32wb55cc.pdf)|
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| Reference Manual | [Reference Manual](https://www.st.com/resource/en/datasheet/stm32wb55cc.pdf) |
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| User Manual | [User Manual](https://www.st.com/content/ccc/resource/technical/document/user_manual/group1/13/58/22/1a/f2/ff/43/5c/DM00517423/files/DM00517423.pdf/jcr:content/translations/en.DM00517423.pdf) |
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Overview
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========
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The p-nucleo-wb55 is a multi-protocol wireless and ultra-low-power
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device embedding a powerful and ultra-low-power radio compliant with the
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Bluetooth® Low Energy (BLE) SIG specification v5.0 and with IEEE
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802.15.4-2011 board. It integrates an ARM Cortex-M4 STM32WB55RG microcontroller
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with 256KB of RAM and 1MB of ROM Flash.
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Flashing the device
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-------------------
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The ST p-nucleo-wb55 board includes an on-board ST-LINK programmer and can be
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flashed using OpenOCD.
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@note The latest release of OpenOCD doesn't contain support for this board,
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so a recent development version must be built from source to be able to flash
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this board.
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To flash this board, just use the following command:
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```
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make BOARD=p-nucleo-wb55 flash -C examples/hello-world
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```
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STDIO
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-----
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STDIO is available via the ST-Link programmer.
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Use the `term` target to open a terminal:
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make BOARD=p-nucleo-wb55 -C examples/hello-world term
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User Interface
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--------------
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4 Button:
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| NAME | RESET/SW4 | SW1 | SW2 | SW3 |
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|:------ |:--------- |:----- |:----- |:----- |
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| Pin | NRST | PC4 | PD0 | PD1 |
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3 LED:
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| NAME | LED1 | LED2 | LED3 |
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| ----- | ------ | ------ | ------ |
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| Color | blue | green | red |
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| Pin | PB5 | PB0 | PB1 |
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Implementation Status
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---------------------
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| Device | ID | Supported | Comments |
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|:---------------- |:----------------- |:------- |:------- |
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| MCU | stm32wb | yes | |
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| | M0+ co-processor | no | |
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| | BLE | no | |
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| | 802.15.4 | no | |
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| Low-level driver | GPIO | yes | |
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| | UART | yes | UART1 |
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| | LPUART | yes | LPUART1 |
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| | I2C | yes | I2C1 |
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| | SPI | yes | |
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| | ADC | yes | |
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| | RTT | yes | |
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| | RTC | yes | |
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| | RNG | yes | |
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| | Timer | yes | TIM2 |
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| | WDT | no | |
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| | USB | no | |
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| | PWM | no | |
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| | AES | no | |
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*/
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73
boards/p-nucleo-wb55/include/arduino_board.h
Normal file
73
boards/p-nucleo-wb55/include/arduino_board.h
Normal file
@ -0,0 +1,73 @@
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/*
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* Copyright (C) 2016 Freie Universität Berlin
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* 2019 Inria
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup boards_p-nucleo-wb55
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* @{
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*
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* @file
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* @brief Board specific configuration for the Arduino API
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*
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* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
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* @author Alexandre Abadie <alexandre.abadie@inria.fr>
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*/
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#ifndef ARDUINO_BOARD_H
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#define ARDUINO_BOARD_H
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#include "arduino_pinmap.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @brief Look-up table for the Arduino's digital pins
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*/
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static const gpio_t arduino_pinmap[] = {
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ARDUINO_PIN_0,
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ARDUINO_PIN_1,
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ARDUINO_PIN_2,
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ARDUINO_PIN_3,
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ARDUINO_PIN_4,
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ARDUINO_PIN_5,
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ARDUINO_PIN_6,
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ARDUINO_PIN_7,
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ARDUINO_PIN_8,
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ARDUINO_PIN_9,
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ARDUINO_PIN_10,
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ARDUINO_PIN_11,
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ARDUINO_PIN_12,
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ARDUINO_PIN_13,
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ARDUINO_PIN_A0,
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ARDUINO_PIN_A1,
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ARDUINO_PIN_A2,
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ARDUINO_PIN_A3,
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ARDUINO_PIN_A4,
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ARDUINO_PIN_A5,
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};
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/**
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* @brief Look-up table for the Arduino's analog pins
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*/
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static const adc_t arduino_analog_map[] = {
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ARDUINO_A0,
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ARDUINO_A1,
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ARDUINO_A2,
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ARDUINO_A3,
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ARDUINO_A4,
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ARDUINO_A5,
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};
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#ifdef __cplusplus
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}
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#endif
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#endif /* ARDUINO_BOARD_H */
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/** @} */
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80
boards/p-nucleo-wb55/include/arduino_pinmap.h
Normal file
80
boards/p-nucleo-wb55/include/arduino_pinmap.h
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@ -0,0 +1,80 @@
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/*
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* Copyright (C) 2019 Inria
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*
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* This file is subject to the terms and conditions of the GNU Lesser
|
||||
* General Public License v2.1. See the file LICENSE in the top level
|
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* directory for more details.
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*/
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/**
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* @ingroup boards_p-nucleo-wb55
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* @{
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*
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* @file
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* @brief Mapping from MCU pins to Arduino pins
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*
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* You can use the defines in this file for simplified interaction with the
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* Arduino specific pin numbers.
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*
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* @author Alexandre Abadie <alexandre.abadie@inria.fr>
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* @author Francisco Molina <francois-xavier.molina@inria.fr>
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*
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*/
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#ifndef ARDUINO_PINMAP_H
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#define ARDUINO_PINMAP_H
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#include "periph/gpio.h"
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#include "periph/adc.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @brief Mapping of MCU pins to Arduino pins
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* @{
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*/
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#define ARDUINO_PIN_0 GPIO_PIN(PORT_A, 3)
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#define ARDUINO_PIN_1 GPIO_PIN(PORT_A, 2)
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#define ARDUINO_PIN_2 GPIO_PIN(PORT_C, 6)
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#define ARDUINO_PIN_3 GPIO_PIN(PORT_A, 10)
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#define ARDUINO_PIN_4 GPIO_PIN(PORT_C, 10)
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#define ARDUINO_PIN_5 GPIO_PIN(PORT_A, 15)
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#define ARDUINO_PIN_6 GPIO_PIN(PORT_A, 8)
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#define ARDUINO_PIN_7 GPIO_PIN(PORT_C, 13)
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#define ARDUINO_PIN_8 GPIO_PIN(PORT_C, 12)
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#define ARDUINO_PIN_9 GPIO_PIN(PORT_A, 9)
|
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#define ARDUINO_PIN_10 GPIO_PIN(PORT_A, 4)
|
||||
#define ARDUINO_PIN_11 GPIO_PIN(PORT_A, 7)
|
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#define ARDUINO_PIN_12 GPIO_PIN(PORT_A, 6)
|
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#define ARDUINO_PIN_13 GPIO_PIN(PORT_A, 5)
|
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#define ARDUINO_PIN_14 GPIO_PIN(PORT_B, 9)
|
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#define ARDUINO_PIN_15 GPIO_PIN(PORT_B, 8)
|
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|
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#define ARDUINO_PIN_A0 GPIO_PIN(PORT_C, 0)
|
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#define ARDUINO_PIN_A1 GPIO_PIN(PORT_C, 1)
|
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#define ARDUINO_PIN_A2 GPIO_PIN(PORT_A, 1)
|
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#define ARDUINO_PIN_A3 GPIO_PIN(PORT_A, 0)
|
||||
#define ARDUINO_PIN_A4 GPIO_PIN(PORT_C, 3)
|
||||
#define ARDUINO_PIN_A5 GPIO_PIN(PORT_C, 2)
|
||||
/** @ */
|
||||
|
||||
/**
|
||||
* @name Mapping of Arduino analog pins to RIOT ADC lines
|
||||
* @{
|
||||
*/
|
||||
#define ARDUINO_A0 ADC_LINE(0)
|
||||
#define ARDUINO_A1 ADC_LINE(1)
|
||||
#define ARDUINO_A2 ADC_LINE(2)
|
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#define ARDUINO_A3 ADC_LINE(3)
|
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#define ARDUINO_A4 ADC_LINE(4)
|
||||
#define ARDUINO_A5 ADC_LINE(5)
|
||||
/** @} */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* ARDUINO_PINMAP_H */
|
||||
/** @} */
|
||||
77
boards/p-nucleo-wb55/include/board.h
Normal file
77
boards/p-nucleo-wb55/include/board.h
Normal file
@ -0,0 +1,77 @@
|
||||
/*
|
||||
* Copyright (C) 2019 Inria
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU Lesser
|
||||
* General Public License v2.1. See the file LICENSE in the top level
|
||||
* directory for more details.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @ingroup boards_p-nucleo-wb55
|
||||
* @{
|
||||
*
|
||||
* @file
|
||||
* @brief Pin definitions and board configuration options
|
||||
*
|
||||
* @author Francisco Molina <francois-xavier.molina@inria.fr>
|
||||
*/
|
||||
|
||||
#ifndef BOARD_H
|
||||
#define BOARD_H
|
||||
|
||||
#include "board_nucleo.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @name LED pin definitions and handlers
|
||||
* @{
|
||||
*/
|
||||
#define LED0_PORT GPIOB
|
||||
#define LED0_PIN GPIO_PIN(PORT_B, 5)
|
||||
#define LED0_MASK (1 << 5)
|
||||
#define LED0_ON (LED0_PORT->BSRR = LED0_MASK)
|
||||
#define LED0_OFF (LED0_PORT->BSRR = (LED0_MASK << 16))
|
||||
#define LED0_TOGGLE (LED0_PORT->ODR ^= LED0_MASK)
|
||||
|
||||
#define LED1_PORT GPIOB
|
||||
#define LED1_PIN GPIO_PIN(PORT_B, 0)
|
||||
#define LED1_MASK (1 << 0)
|
||||
#define LED1_ON (LED0_PORT->BSRR = LED1_MASK)
|
||||
#define LED1_OFF (LED0_PORT->BSRR = (LED1_MASK << 16))
|
||||
#define LED1_TOGGLE (LED0_PORT->ODR ^= LED1_MASK)
|
||||
|
||||
#define LED2_PORT GPIOB
|
||||
#define LED2_PIN GPIO_PIN(PORT_B, 1)
|
||||
#define LED2_MASK (1 << 1)
|
||||
#define LED2_ON (LED0_PORT->BSRR = LED2_MASK)
|
||||
#define LED2_OFF (LED0_PORT->BSRR = (LED2_MASK << 16))
|
||||
#define LED2_TOGGLE (LED0_PORT->ODR ^= LED2_MASK)
|
||||
/** @} */
|
||||
|
||||
/* p-nucleo-wb55 always use LED0, as there is no dual use of its pin */
|
||||
#ifndef AUTO_INIT_LED0
|
||||
#define AUTO_INIT_LED0
|
||||
#endif
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name User button
|
||||
* @{
|
||||
*/
|
||||
#define BTN0_PIN GPIO_PIN(PORT_C, 4)
|
||||
#define BTN0_MODE GPIO_IN_PU
|
||||
#define BTN1_PIN GPIO_PIN(PORT_D, 0)
|
||||
#define BTN1_MODE GPIO_IN_PU
|
||||
#define BTN2_PIN GPIO_PIN(PORT_D, 1)
|
||||
#define BTN2_MODE GPIO_IN_PU
|
||||
/** @} */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* BOARD_H */
|
||||
/** @} */
|
||||
78
boards/p-nucleo-wb55/include/gpio_params.h
Normal file
78
boards/p-nucleo-wb55/include/gpio_params.h
Normal file
@ -0,0 +1,78 @@
|
||||
/*
|
||||
* Copyright (C) 2019 Inria
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU Lesser
|
||||
* General Public License v2.1. See the file LICENSE in the top level
|
||||
* directory for more details.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @ingroup boards_p-nucleo-wb55
|
||||
* @{
|
||||
*
|
||||
* @file
|
||||
* @brief Board specific configuration of direct mapped GPIOs
|
||||
*
|
||||
* @author Alexandre Abadie <alexandre.abadie@inria.fr>
|
||||
* @author Francisco Molina <francois-xavier.molina@inria.fr>
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef GPIO_PARAMS_H
|
||||
#define GPIO_PARAMS_H
|
||||
|
||||
#include "board.h"
|
||||
#include "saul/periph.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief GPIO pin configuration
|
||||
*/
|
||||
static const saul_gpio_params_t saul_gpio_params[] =
|
||||
{
|
||||
#ifdef AUTO_INIT_LED0
|
||||
{
|
||||
.name = "LED(blue)",
|
||||
.pin = LED0_PIN,
|
||||
.mode = GPIO_OUT
|
||||
},
|
||||
#endif
|
||||
{
|
||||
.name = "LED(green)",
|
||||
.pin = LED1_PIN,
|
||||
.mode = GPIO_OUT
|
||||
},
|
||||
{
|
||||
.name = "LED(red)",
|
||||
.pin = LED2_PIN,
|
||||
.mode = GPIO_OUT
|
||||
},
|
||||
{
|
||||
.name = "Button(B1 User)",
|
||||
.pin = BTN0_PIN,
|
||||
.mode = BTN0_MODE,
|
||||
.flags = SAUL_GPIO_INVERTED,
|
||||
},
|
||||
{
|
||||
.name = "Button(B2 User)",
|
||||
.pin = BTN1_PIN,
|
||||
.mode = BTN1_MODE,
|
||||
.flags = SAUL_GPIO_INVERTED,
|
||||
},
|
||||
{
|
||||
.name = "Button(B3 User)",
|
||||
.pin = BTN2_PIN,
|
||||
.mode = BTN2_MODE,
|
||||
.flags = SAUL_GPIO_INVERTED,
|
||||
},
|
||||
};
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* GPIO_PARAMS_H */
|
||||
/** @} */
|
||||
175
boards/p-nucleo-wb55/include/periph_conf.h
Normal file
175
boards/p-nucleo-wb55/include/periph_conf.h
Normal file
@ -0,0 +1,175 @@
|
||||
/*
|
||||
* Copyright (C) 2019 Inria
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU Lesser
|
||||
* General Public License v2.1. See the file LICENSE in the top level
|
||||
* directory for more details.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @ingroup boards_p-nucleo-wb55
|
||||
* @{
|
||||
*
|
||||
* @file
|
||||
* @brief Peripheral MCU configuration for the p-nucleo-wb55 board
|
||||
*
|
||||
* @author Francisco Molina <francois-xavier.molina@inria.fr>
|
||||
*/
|
||||
|
||||
|
||||
#ifndef PERIPH_CONF_H
|
||||
#define PERIPH_CONF_H
|
||||
|
||||
#include "periph_cpu.h"
|
||||
#include "cfg_i2c1_pb8_pb9.h"
|
||||
#include "cfg_rtt_default.h"
|
||||
#include "cfg_timer_tim2.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @name Clock system configuration
|
||||
* @{
|
||||
*/
|
||||
/* 0: no external high speed crystal available
|
||||
* else: actual crystal frequency [in Hz] */
|
||||
#define CLOCK_HSE (32000000U)
|
||||
|
||||
#ifndef CLOCK_LSE
|
||||
/* 0: no external low speed crystal available,
|
||||
* 1: external crystal available (always 32.768kHz)
|
||||
*/
|
||||
#define CLOCK_LSE (1)
|
||||
#endif
|
||||
|
||||
/* 0: enable MSI only if HSE isn't available
|
||||
* 1: always enable MSI (e.g. if USB or RNG is used)*/
|
||||
#define CLOCK_MSI_ENABLE (1)
|
||||
|
||||
#ifndef CLOCK_MSI_LSE_PLL
|
||||
/* 0: disable Hardware auto calibration with LSE
|
||||
* 1: enable Hardware auto calibration with LSE (PLL-mode)
|
||||
*/
|
||||
#define CLOCK_MSI_LSE_PLL (1)
|
||||
#endif
|
||||
|
||||
/* give the target core clock (HCLK) frequency [in Hz], maximum: 64MHz */
|
||||
#define CLOCK_CORECLOCK (64000000U)
|
||||
/* PLL configuration: make sure your values are legit!
|
||||
*
|
||||
* compute by: CORECLOCK = (((PLL_IN / M) * N) / R)
|
||||
* with:
|
||||
* PLL_IN: input clock, HSE or MSI @ 48MHz
|
||||
* M: pre-divider, allowed range: [1:8]
|
||||
* N: multiplier, allowed range: [8:86]
|
||||
* R: post-divider, allowed range: [2:8]
|
||||
*
|
||||
* Also the following constraints need to be met:
|
||||
* (PLL_IN / M) -> [4MHz:16MHz]
|
||||
* (PLL_IN / M) * N -> [64MHz:344MHz]
|
||||
* CORECLOCK -> 64MHz MAX!
|
||||
*/
|
||||
#define CLOCK_PLL_M (4)
|
||||
#define CLOCK_PLL_N (32)
|
||||
#define CLOCK_PLL_R (4)
|
||||
|
||||
/* EXTAHB (HCLK2) max freq 32 Mhz*/
|
||||
#define CLOCK_EXTAHB_DIV RCC_EXTCFGR_C2HPRE_3
|
||||
#define CLOCK_EXTAHB (CLOCK_CORECLOCK / 2)
|
||||
/* peripheral clock setup */
|
||||
#define CLOCK_AHB_DIV 0x00000000U
|
||||
#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
|
||||
#define CLOCK_APB1_DIV 0x00000000U
|
||||
#define CLOCK_APB1 (CLOCK_CORECLOCK / 1)
|
||||
#define CLOCK_APB2_DIV 0x00000000U
|
||||
#define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name UART configuration
|
||||
* @{
|
||||
*/
|
||||
static const uart_conf_t uart_config[] = {
|
||||
{
|
||||
.dev = USART1,
|
||||
.rcc_mask = RCC_APB2ENR_USART1EN,
|
||||
.rx_pin = GPIO_PIN(PORT_B, 7),
|
||||
.tx_pin = GPIO_PIN(PORT_B, 6),
|
||||
.rx_af = GPIO_AF7,
|
||||
.tx_af = GPIO_AF7,
|
||||
.bus = APB2,
|
||||
.irqn = USART1_IRQn,
|
||||
.type = STM32_USART,
|
||||
.clk_src = 0, /* Use APB clock */
|
||||
},
|
||||
{
|
||||
.dev = LPUART1,
|
||||
.rcc_mask = RCC_APB1ENR2_LPUART1EN,
|
||||
.rx_pin = GPIO_PIN(PORT_A, 3),
|
||||
.tx_pin = GPIO_PIN(PORT_A, 2),
|
||||
.rx_af = GPIO_AF8,
|
||||
.tx_af = GPIO_AF8,
|
||||
.bus = APB12,
|
||||
.irqn = LPUART1_IRQn,
|
||||
.type = STM32_LPUART,
|
||||
.clk_src = 0, /* Use APB clock */
|
||||
},
|
||||
};
|
||||
|
||||
#define UART_0_ISR (isr_usart1)
|
||||
#define UART_1_ISR (isr_lpuart1)
|
||||
|
||||
#define UART_NUMOF ARRAY_SIZE(uart_config)
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name SPI configuration
|
||||
*
|
||||
* @note The spi_divtable is auto-generated from
|
||||
* `cpu/stm32_common/dist/spi_divtable/spi_divtable.c`
|
||||
* @{
|
||||
*/
|
||||
static const uint8_t spi_divtable[2][5] = {
|
||||
{ /* for APB1 @ 20000000Hz */
|
||||
7, /* -> 78125Hz */
|
||||
5, /* -> 312500Hz */
|
||||
3, /* -> 1250000Hz */
|
||||
1, /* -> 5000000Hz */
|
||||
0 /* -> 10000000Hz */
|
||||
},
|
||||
{ /* for APB2 @ 40000000Hz */
|
||||
7, /* -> 156250Hz */
|
||||
6, /* -> 312500Hz */
|
||||
4, /* -> 1250000Hz */
|
||||
2, /* -> 5000000Hz */
|
||||
1 /* -> 10000000Hz */
|
||||
}
|
||||
};
|
||||
|
||||
static const spi_conf_t spi_config[] = {
|
||||
{
|
||||
.dev = SPI1,
|
||||
.mosi_pin = GPIO_PIN(PORT_A, 7),
|
||||
.miso_pin = GPIO_PIN(PORT_A, 6),
|
||||
.sclk_pin = GPIO_PIN(PORT_A, 5),
|
||||
.cs_pin = GPIO_UNDEF,
|
||||
.mosi_af = GPIO_AF5,
|
||||
.miso_af = GPIO_AF5,
|
||||
.sclk_af = GPIO_AF5,
|
||||
.cs_af = GPIO_AF5,
|
||||
.rccmask = RCC_APB2ENR_SPI1EN,
|
||||
.apbbus = APB2,
|
||||
}
|
||||
};
|
||||
|
||||
#define SPI_NUMOF ARRAY_SIZE(spi_config)
|
||||
/** @} */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* PERIPH_CONF_H */
|
||||
/** @} */
|
||||
Loading…
Reference in New Issue
Block a user