From e1df626a9ba6518e8910e13e30917a6ae06c0540 Mon Sep 17 00:00:00 2001 From: Hauke Petersen Date: Tue, 26 Jan 2016 22:48:12 +0100 Subject: [PATCH] cpu/cc2538: doxgen fixes - added missing documentation - repaired doxygen groups --- cpu/cc2538/doc.txt | 5 +- cpu/cc2538/include/cc2538.h | 2 +- cpu/cc2538/include/cc2538_gpio.h | 20 +-- cpu/cc2538/include/cc2538_gptimer.h | 178 ++++++++++++++------------- cpu/cc2538/include/cc2538_ioc.h | 29 ++--- cpu/cc2538/include/cc2538_rfcore.h | 13 +- cpu/cc2538/include/cc2538_soc_adc.h | 7 +- cpu/cc2538/include/cc2538_sys_ctrl.h | 19 ++- cpu/cc2538/include/cc2538_uart.h | 24 +++- 9 files changed, 178 insertions(+), 119 deletions(-) diff --git a/cpu/cc2538/doc.txt b/cpu/cc2538/doc.txt index 06e55df03d..8ae0c368b1 100644 --- a/cpu/cc2538/doc.txt +++ b/cpu/cc2538/doc.txt @@ -1,10 +1,11 @@ /** - * @defgroup cpu_cc2538 Texas Instruments CC2538 + * @defgroup cpu_cc2538 TI CC2538 * @ingroup cpu * @brief Texas Instruments CC2538 Cortex-M3 MCU specific code */ /** - * @defgroup cpu_cc2538_definitions Texas Instruments CC2538 Definitions + * @defgroup cpu_cc2538_regs TI CC2538 CMSIS-style Headers * @ingroup cpu_cc2538 + * @brief CMSIS-style register definitions for the TI CC2538 */ diff --git a/cpu/cc2538/include/cc2538.h b/cpu/cc2538/include/cc2538.h index f992f86344..b74c20bd4a 100644 --- a/cpu/cc2538/include/cc2538.h +++ b/cpu/cc2538/include/cc2538.h @@ -7,7 +7,7 @@ */ /** - * @ingroup cpu_cc2538_definitions + * @ingroup cpu_cc2538_regs * @{ * * @file diff --git a/cpu/cc2538/include/cc2538_gpio.h b/cpu/cc2538/include/cc2538_gpio.h index a286534b42..adf27bb71e 100644 --- a/cpu/cc2538/include/cc2538_gpio.h +++ b/cpu/cc2538/include/cc2538_gpio.h @@ -7,7 +7,8 @@ */ /** - * @addtogroup cpu_cc2538 + * @defgroup cpu_cc2538_gpio CC2538 General-Purpose I/O + * @ingroup cpu_cc2538_regs * @{ * * @file @@ -17,7 +18,6 @@ * * @author Ian Martin * - * @defgroup cc2538-gpio CC2538 General-Purpose I/O * @{ */ @@ -216,14 +216,14 @@ typedef struct { * @brief IOC port component registers */ typedef struct { - cc2538_reg_t PA_SEL[8]; - cc2538_reg_t PB_SEL[8]; - cc2538_reg_t PC_SEL[8]; - cc2538_reg_t PD_SEL[8]; - cc2538_reg_t PA_OVER[8]; - cc2538_reg_t PB_OVER[8]; - cc2538_reg_t PC_OVER[8]; - cc2538_reg_t PD_OVER[8]; + cc2538_reg_t PA_SEL[8]; /**< Port A SEL register */ + cc2538_reg_t PB_SEL[8]; /**< Port B SEL register */ + cc2538_reg_t PC_SEL[8]; /**< Port C SEL register */ + cc2538_reg_t PD_SEL[8]; /**< Port D SEL register */ + cc2538_reg_t PA_OVER[8]; /**< Port A OVER register */ + cc2538_reg_t PB_OVER[8]; /**< Port B OVER register */ + cc2538_reg_t PC_OVER[8]; /**< Port C OVER register */ + cc2538_reg_t PD_OVER[8]; /**< Port D OVER register */ } cc2538_ioc_t; /** diff --git a/cpu/cc2538/include/cc2538_gptimer.h b/cpu/cc2538/include/cc2538_gptimer.h index f90c5f90d7..0aa4316ee6 100644 --- a/cpu/cc2538/include/cc2538_gptimer.h +++ b/cpu/cc2538/include/cc2538_gptimer.h @@ -7,7 +7,8 @@ */ /** - * @addtogroup cpu_cc2538 + * @defgroup cpu_cc2538_gptimer CC2538 General Purpose Timer + * @ingroup cpu_cc2538_regs * @{ * * @file @@ -27,108 +28,117 @@ extern "C" { #endif -#define GPTIMER_NUMOF 4 /**< The CC2538 has four general-purpose timer units. */ -#define NUM_CHANNELS_PER_GPTIMER 2 /**< Each G.P. timer unit has two channels: A and B. */ +#define GPTIMER_NUMOF 4 /**< The CC2538 has four general-purpose timer units. */ +#define NUM_CHANNELS_PER_GPTIMER 2 /**< Each G.P. timer unit has two channels: A and B. */ enum { - GPTIMER_ONE_SHOT_MODE = 1, /**< GPTIMER one-shot mode */ - GPTIMER_PERIODIC_MODE = 2, /**< GPTIMER periodic mode */ - GPTIMER_CAPTURE_MODE = 3, /**< GPTIMER capture mode */ + GPTIMER_ONE_SHOT_MODE = 1, /**< GPTIMER one-shot mode */ + GPTIMER_PERIODIC_MODE = 2, /**< GPTIMER periodic mode */ + GPTIMER_CAPTURE_MODE = 3, /**< GPTIMER capture mode */ }; enum { - GPTMCFG_32_BIT_TIMER = 0, /**< 32-bit timer configuration */ - GPTMCFG_32_BIT_REAL_TIME_CLOCK = 1, /**< 32-bit real-time clock */ - GPTMCFG_16_BIT_TIMER = 4, /**< 16-bit timer configuration */ + GPTMCFG_32_BIT_TIMER = 0, /**< 32-bit timer configuration */ + GPTMCFG_32_BIT_REAL_TIME_CLOCK = 1, /**< 32-bit real-time clock */ + GPTMCFG_16_BIT_TIMER = 4, /**< 16-bit timer configuration */ }; /** * @brief GPTIMER component registers */ typedef struct { - cc2538_reg_t CFG; /**< GPTIMER Configuration */ + cc2538_reg_t CFG; /**< GPTIMER Configuration */ + /** + * @brief Timer A + */ union { - cc2538_reg_t TAMR; /**< GPTIMER Timer A mode */ + cc2538_reg_t TAMR; /**< GPTIMER Timer A mode */ struct { - cc2538_reg_t TAMR2 : 2; /**< GPTM Timer A mode */ - cc2538_reg_t TACRM : 1; /**< GPTM Timer A capture mode */ - cc2538_reg_t TAAMS : 1; /**< GPTM Timer A alternate mode */ - cc2538_reg_t TACDIR : 1; /**< GPTM Timer A count direction */ - cc2538_reg_t TAMIE : 1; /**< GPTM Timer A match interrupt enable */ - cc2538_reg_t TAWOT : 1; /**< GPTM Timer A wait-on-trigger */ - cc2538_reg_t TASNAPS : 1; /**< GPTM Timer A snap shot mode */ - cc2538_reg_t TAILD : 1; /**< GPTM Timer A interval load write */ - cc2538_reg_t TAPWMIE : 1; /**< GPTM Timer A PWM interrupt enable */ - cc2538_reg_t TAMRSU : 1; /**< Timer A match register update mode */ - cc2538_reg_t TAPLO : 1; /**< Legacy PWM operation */ - cc2538_reg_t RESERVED5 : 20; /**< Reserved bits */ + cc2538_reg_t TAMR2 : 2; /**< GPTM Timer A mode */ + cc2538_reg_t TACRM : 1; /**< GPTM Timer A capture mode */ + cc2538_reg_t TAAMS : 1; /**< GPTM Timer A alternate mode */ + cc2538_reg_t TACDIR : 1; /**< GPTM Timer A count direction */ + cc2538_reg_t TAMIE : 1; /**< GPTM Timer A match interrupt enable */ + cc2538_reg_t TAWOT : 1; /**< GPTM Timer A wait-on-trigger */ + cc2538_reg_t TASNAPS : 1; /**< GPTM Timer A snap shot mode */ + cc2538_reg_t TAILD : 1; /**< GPTM Timer A interval load write */ + cc2538_reg_t TAPWMIE : 1; /**< GPTM Timer A PWM interrupt enable */ + cc2538_reg_t TAMRSU : 1; /**< Timer A match register update mode */ + cc2538_reg_t TAPLO : 1; /**< Legacy PWM operation */ + cc2538_reg_t RESERVED5 : 20; /**< Reserved bits */ } TAMRbits; } cc2538_gptimer_tamr; + /** + * @brief Timer B + */ union { - cc2538_reg_t TBMR; /**< GPTIMER Timer B mode */ + cc2538_reg_t TBMR; /**< GPTIMER Timer B mode */ struct { - cc2538_reg_t TBMR2 : 2; /**< GPTM Timer B mode */ - cc2538_reg_t TBCRM : 1; /**< GPTM Timer B capture mode */ - cc2538_reg_t TBAMS : 1; /**< GPTM Timer B alternate mode */ - cc2538_reg_t TBCDIR : 1; /**< GPTM Timer B count direction */ - cc2538_reg_t TBMIE : 1; /**< GPTM Timer B match interrupt enable */ - cc2538_reg_t TBWOT : 1; /**< GPTM Timer B wait-on-trigger */ - cc2538_reg_t TBSNAPS : 1; /**< GPTM Timer B snap shot mode */ - cc2538_reg_t TBILD : 1; /**< GPTM Timer B interval load write */ - cc2538_reg_t TBPWMIE : 1; /**< GPTM Timer B PWM interrupt enable */ - cc2538_reg_t TBMRSU : 1; /**< Timer B match register update mode */ - cc2538_reg_t TBPLO : 1; /**< Legacy PWM operation */ - cc2538_reg_t RESERVED6 : 20; /**< Reserved bits */ + cc2538_reg_t TBMR2 : 2; /**< GPTM Timer B mode */ + cc2538_reg_t TBCRM : 1; /**< GPTM Timer B capture mode */ + cc2538_reg_t TBAMS : 1; /**< GPTM Timer B alternate mode */ + cc2538_reg_t TBCDIR : 1; /**< GPTM Timer B count direction */ + cc2538_reg_t TBMIE : 1; /**< GPTM Timer B match interrupt enable */ + cc2538_reg_t TBWOT : 1; /**< GPTM Timer B wait-on-trigger */ + cc2538_reg_t TBSNAPS : 1; /**< GPTM Timer B snap shot mode */ + cc2538_reg_t TBILD : 1; /**< GPTM Timer B interval load write */ + cc2538_reg_t TBPWMIE : 1; /**< GPTM Timer B PWM interrupt enable */ + cc2538_reg_t TBMRSU : 1; /**< Timer B match register update mode */ + cc2538_reg_t TBPLO : 1; /**< Legacy PWM operation */ + cc2538_reg_t RESERVED6 : 20; /**< Reserved bits */ } TBMRbits; } cc2538_gptimer_tbmr; + /** + * @brief Timer Control + */ union { - cc2538_reg_t CTL; /**< GPTIMER Control */ + cc2538_reg_t CTL; /**< GPTIMER Control */ struct { - cc2538_reg_t TAEN : 1; /**< GPTM Timer A enable */ - cc2538_reg_t TASTALL : 1; /**< GPTM Timer A stall enable */ - cc2538_reg_t TAEVENT : 1; /**< GPTM Timer A event mode */ - cc2538_reg_t RESERVED1 : 1; /**< Reserved bits */ - cc2538_reg_t TAOTE : 1; /**< GPTM Timer A PWM output trigger enable */ - cc2538_reg_t TAPWML : 1; /**< GPTM Timer A PWM output level */ - cc2538_reg_t RESERVED2 : 1; /**< Reserved bits */ - cc2538_reg_t TBEN : 1; /**< GPTM Timer B enable */ - cc2538_reg_t TBSTALL : 1; /**< GPTM Timer B stall enable */ - cc2538_reg_t TBEVENT : 1; /**< GPTM Timer B event mode */ - cc2538_reg_t RESERVED3 : 1; /**< Reserved bits */ - cc2538_reg_t TBOTE : 1; /**< GPTM Timer B PWM output trigger enable */ - cc2538_reg_t TBPWML : 1; /**< GPTM Timer B PWM output level */ - cc2538_reg_t RESERVED4 : 17; /**< Reserved bits */ + cc2538_reg_t TAEN : 1; /**< GPTM Timer A enable */ + cc2538_reg_t TASTALL : 1; /**< GPTM Timer A stall enable */ + cc2538_reg_t TAEVENT : 1; /**< GPTM Timer A event mode */ + cc2538_reg_t RESERVED1 : 1; /**< Reserved bits */ + cc2538_reg_t TAOTE : 1; /**< GPTM Timer A PWM output trigger enable */ + cc2538_reg_t TAPWML : 1; /**< GPTM Timer A PWM output level */ + cc2538_reg_t RESERVED2 : 1; /**< Reserved bits */ + cc2538_reg_t TBEN : 1; /**< GPTM Timer B enable */ + cc2538_reg_t TBSTALL : 1; /**< GPTM Timer B stall enable */ + cc2538_reg_t TBEVENT : 1; /**< GPTM Timer B event mode */ + cc2538_reg_t RESERVED3 : 1; /**< Reserved bits */ + cc2538_reg_t TBOTE : 1; /**< GPTM Timer B PWM output trigger enable */ + cc2538_reg_t TBPWML : 1; /**< GPTM Timer B PWM output level */ + cc2538_reg_t RESERVED4 : 17; /**< Reserved bits */ } CTLbits; } cc2538_gptimer_ctl; - cc2538_reg_t SYNC; /**< GPTIMER Synchronize */ - cc2538_reg_t RESERVED2; /**< Reserved word */ - cc2538_reg_t IMR; /**< GPTIMER Interrupt Mask */ - cc2538_reg_t RIS; /**< GPTIMER Raw Interrupt Status */ - cc2538_reg_t MIS; /**< GPTIMER Masked Interrupt Status */ - cc2538_reg_t ICR; /**< GPTIMER Interrupt Clear */ - cc2538_reg_t TAILR; /**< GPTIMER Timer A Interval Load */ - cc2538_reg_t TBILR; /**< GPTIMER Timer B Interval Load */ - cc2538_reg_t TAMATCHR; /**< GPTIMER Timer A Match */ - cc2538_reg_t TBMATCHR; /**< GPTIMER Timer B Match */ - cc2538_reg_t TAPR; /**< GPTIMER Timer A Prescale Register */ - cc2538_reg_t TBPR; /**< GPTIMER Timer B Prescale Register */ - cc2538_reg_t TAPMR; /**< GPTIMER Timer A Prescale Match Register */ - cc2538_reg_t TBPMR; /**< GPTIMER Timer B Prescale Match Register */ - cc2538_reg_t TAR; /**< GPTIMER Timer A */ - cc2538_reg_t TBR; /**< GPTIMER Timer B */ - cc2538_reg_t TAV; /**< GPTIMER Timer A Value */ - cc2538_reg_t TBV; /**< GPTIMER Timer B Value */ - cc2538_reg_t RESERVED3; /**< Reserved word */ - cc2538_reg_t TAPS; /**< GPTIMER Timer A Prescale Snapshot */ - cc2538_reg_t TBPS; /**< GPTIMER Timer B Prescale Snapshot */ - cc2538_reg_t TAPV; /**< GPTIMER Timer A Prescale Value */ - cc2538_reg_t TBPV; /**< GPTIMER Timer B Prescale Value */ - cc2538_reg_t RESERVED[981]; - cc2538_reg_t PP; /**< GPTIMER Peripheral Properties */ + cc2538_reg_t SYNC; /**< GPTIMER Synchronize */ + cc2538_reg_t RESERVED2; /**< Reserved word */ + cc2538_reg_t IMR; /**< GPTIMER Interrupt Mask */ + cc2538_reg_t RIS; /**< GPTIMER Raw Interrupt Status */ + cc2538_reg_t MIS; /**< GPTIMER Masked Interrupt Status */ + cc2538_reg_t ICR; /**< GPTIMER Interrupt Clear */ + cc2538_reg_t TAILR; /**< GPTIMER Timer A Interval Load */ + cc2538_reg_t TBILR; /**< GPTIMER Timer B Interval Load */ + cc2538_reg_t TAMATCHR; /**< GPTIMER Timer A Match */ + cc2538_reg_t TBMATCHR; /**< GPTIMER Timer B Match */ + cc2538_reg_t TAPR; /**< GPTIMER Timer A Prescale Register */ + cc2538_reg_t TBPR; /**< GPTIMER Timer B Prescale Register */ + cc2538_reg_t TAPMR; /**< GPTIMER Timer A Prescale Match Register */ + cc2538_reg_t TBPMR; /**< GPTIMER Timer B Prescale Match Register */ + cc2538_reg_t TAR; /**< GPTIMER Timer A */ + cc2538_reg_t TBR; /**< GPTIMER Timer B */ + cc2538_reg_t TAV; /**< GPTIMER Timer A Value */ + cc2538_reg_t TBV; /**< GPTIMER Timer B Value */ + cc2538_reg_t RESERVED3; /**< Reserved word */ + cc2538_reg_t TAPS; /**< GPTIMER Timer A Prescale Snapshot */ + cc2538_reg_t TBPS; /**< GPTIMER Timer B Prescale Snapshot */ + cc2538_reg_t TAPV; /**< GPTIMER Timer A Prescale Value */ + cc2538_reg_t TBPV; /**< GPTIMER Timer B Prescale Value */ + cc2538_reg_t RESERVED[981]; /**< Reserved */ + cc2538_reg_t PP; /**< GPTIMER Peripheral Properties */ } cc2538_gptimer_t; #define GPTIMER0 ( (cc2538_gptimer_t*)0x40030000 ) /**< GPTIMER0 Instance */ @@ -136,14 +146,14 @@ typedef struct { #define GPTIMER2 ( (cc2538_gptimer_t*)0x40032000 ) /**< GPTIMER2 Instance */ #define GPTIMER3 ( (cc2538_gptimer_t*)0x40033000 ) /**< GPTIMER3 Instance */ -void isr_timer0_chan0(void); /**< RIOT Timer 0 Channel 0 Interrupt Service Routine */ -void isr_timer0_chan1(void); /**< RIOT Timer 0 Channel 1 Interrupt Service Routine */ -void isr_timer1_chan0(void); /**< RIOT Timer 1 Channel 0 Interrupt Service Routine */ -void isr_timer1_chan1(void); /**< RIOT Timer 1 Channel 1 Interrupt Service Routine */ -void isr_timer2_chan0(void); /**< RIOT Timer 2 Channel 0 Interrupt Service Routine */ -void isr_timer2_chan1(void); /**< RIOT Timer 2 Channel 1 Interrupt Service Routine */ -void isr_timer3_chan0(void); /**< RIOT Timer 3 Channel 0 Interrupt Service Routine */ -void isr_timer3_chan1(void); /**< RIOT Timer 3 Channel 1 Interrupt Service Routine */ +void isr_timer0_chan0(void); /**< RIOT Timer 0 Channel 0 Interrupt Service Routine */ +void isr_timer0_chan1(void); /**< RIOT Timer 0 Channel 1 Interrupt Service Routine */ +void isr_timer1_chan0(void); /**< RIOT Timer 1 Channel 0 Interrupt Service Routine */ +void isr_timer1_chan1(void); /**< RIOT Timer 1 Channel 1 Interrupt Service Routine */ +void isr_timer2_chan0(void); /**< RIOT Timer 2 Channel 0 Interrupt Service Routine */ +void isr_timer2_chan1(void); /**< RIOT Timer 2 Channel 1 Interrupt Service Routine */ +void isr_timer3_chan0(void); /**< RIOT Timer 3 Channel 0 Interrupt Service Routine */ +void isr_timer3_chan1(void); /**< RIOT Timer 3 Channel 1 Interrupt Service Routine */ #ifdef __cplusplus } /* end extern "C" */ diff --git a/cpu/cc2538/include/cc2538_ioc.h b/cpu/cc2538/include/cc2538_ioc.h index 3a6838bf5e..58abceea04 100644 --- a/cpu/cc2538/include/cc2538_ioc.h +++ b/cpu/cc2538/include/cc2538_ioc.h @@ -7,23 +7,21 @@ */ /** + * @defgroup cpu_cc2538_ioc CC2538 I/O Control + * @ingroup cpu_cc2538_regs * @{ * * @file * @brief CC2538 I/O Control driver * + * Header file with declarations for the I/O Control module + * * @author Ian Martin * - * @addtogroup cpu_cc2538 - * @{ - * - * @defgroup cc2538-ioc CC2538 I/O Control - * - * Header file with declarations for the I/O Control module - * @{ */ -#ifndef IOC_H_ -#define IOC_H_ + +#ifndef CC2538_IOC_H_ +#define CC2538_IOC_H_ #include @@ -33,8 +31,13 @@ extern "C" { #endif +/** + * @name Port control register addresses + * @{ + */ #define IOC_PXX_SEL ( (cc2538_reg_t*)0x400d4000 ) #define IOC_PXX_OVER ( (cc2538_reg_t*)0x400d4080 ) +/** @} */ /** @name Peripheral Signal Select Values (for IOC_Pxx_SEL registers) * @{ @@ -64,7 +67,8 @@ enum { }; /** @} */ -/** @name Values for IOC_PXX_OVER +/** + * @name Values for IOC_PXX_OVER * @{ */ #define IOC_OVERRIDE_OE 0x00000008 /**< Output Enable */ @@ -78,8 +82,5 @@ enum { } /* end extern "C" */ #endif -#endif /* IOC_H_ */ - -/** @} */ -/** @} */ +#endif /* CC2538_IOC_H_ */ /** @} */ diff --git a/cpu/cc2538/include/cc2538_rfcore.h b/cpu/cc2538/include/cc2538_rfcore.h index fa82e5808d..3da96c5b9f 100644 --- a/cpu/cc2538/include/cc2538_rfcore.h +++ b/cpu/cc2538/include/cc2538_rfcore.h @@ -7,6 +7,8 @@ */ /** + * @defgroup cpu_cc2538_rfcore CC2538 RF core interface + * @ingroup cpu_cc2538_regs * @{ * * @file @@ -14,11 +16,6 @@ * * @author Ian Martin * - * @addtogroup cpu_cc2538 - * @{ - * - * @defgroup cc2538-rfcore CC2538 RF core interface - * @{ */ #ifndef CC2538_RFCORE_H @@ -83,6 +80,9 @@ typedef struct { cc2538_reg_t XREG_CCACTRL1; /**< RF Other CCA Options */ cc2538_reg_t XREG_RSSI; /**< RF RSSI status register */ + /** + * @brief RSSI status register + */ union { cc2538_reg_t XREG_RSSISTAT; /**< RF RSSI valid status register */ struct { @@ -105,6 +105,9 @@ typedef struct { cc2538_reg_t XREG_RFERRM; /**< RF error interrupt mask */ cc2538_reg_t RESERVED3; /**< Reserved bytes */ + /** + * @brief RF random data register + */ union { cc2538_reg_t XREG_RFRND; /**< RF Random data */ struct { diff --git a/cpu/cc2538/include/cc2538_soc_adc.h b/cpu/cc2538/include/cc2538_soc_adc.h index 5adf6cac0a..0caf3f7e76 100644 --- a/cpu/cc2538/include/cc2538_soc_adc.h +++ b/cpu/cc2538/include/cc2538_soc_adc.h @@ -7,7 +7,8 @@ */ /** - * @ingroup cpu_cc2538 + * @defgroup cpu_cc2538_adc CC2538 ADC + * @ingroup cpu_cc2538_regs * @{ * * @file @@ -29,6 +30,10 @@ extern "C" { * @brief SOC ADC component registers */ typedef struct { + + /** + * @brief ADC control register + */ union { cc2538_reg_t ADCCON1; /**< ADC Control Register 1 */ struct { diff --git a/cpu/cc2538/include/cc2538_sys_ctrl.h b/cpu/cc2538/include/cc2538_sys_ctrl.h index bf2340db87..65dfc659f5 100644 --- a/cpu/cc2538/include/cc2538_sys_ctrl.h +++ b/cpu/cc2538/include/cc2538_sys_ctrl.h @@ -7,7 +7,8 @@ */ /** - * @ingroup cpu_cc2538 + * @defgroup cpu_cc2538_sysctrl CC2538 System Control + * @ingroup cpu_cc2538_regs * @{ * * @file @@ -29,6 +30,10 @@ extern "C" { * @brief System Control component registers */ typedef struct { + + /** + * @brief Clock control register + */ union { cc2538_reg_t CLOCK_CTRL; /**< Clock control register */ struct { @@ -47,6 +52,9 @@ typedef struct { } CLOCK_CTRLbits; } cc2538_sys_ctrl_clk_ctrl; + /** + * @brief Clock status register + */ union { cc2538_reg_t CLOCK_STA; /**< Clock status register */ struct { @@ -77,6 +85,9 @@ typedef struct { cc2538_reg_t DCGCSSI; /**< Module clocks for SSI[1:0] when the CPU is in PM0 */ cc2538_reg_t SRSSI; /**< Reset for SSI[1:0]. */ + /** + * @brief UART module clock register - active mode + */ union { cc2538_reg_t RCGCUART; /**< Module clocks for UART[1:0] when the CPU is in active (run) mode */ struct { @@ -86,6 +97,9 @@ typedef struct { } RCGCUARTbits; } cc2538_sys_ctrl_unnamed1; + /** + * @brief UART module clock register - sleep mode + */ union { cc2538_reg_t SCGCUART; /**< Module clocks for UART[1:0] when the CPU is in sleep mode */ struct { @@ -95,6 +109,9 @@ typedef struct { } SCGCUARTbits; } cc2538_sys_ctrl_unnamed2; + /** + * @brief UART module clock register - PM0 mode + */ union { cc2538_reg_t DCGCUART; /**< Module clocks for UART[1:0] when the CPU is in PM0 */ struct { diff --git a/cpu/cc2538/include/cc2538_uart.h b/cpu/cc2538/include/cc2538_uart.h index 46c5977763..0fd671a983 100644 --- a/cpu/cc2538/include/cc2538_uart.h +++ b/cpu/cc2538/include/cc2538_uart.h @@ -7,7 +7,8 @@ */ /** - * @addtogroup cpu_cc2538 + * @defgroup cpu_cc2538_uart CC2538 UART + * @ingroup cpu_cc2538_regs * @{ * * @file @@ -31,6 +32,9 @@ extern "C" { typedef struct { cc2538_reg_t DR; /**< UART Data Register */ + /** + * @brief Status register + */ union { cc2538_reg_t RSR; /**< UART receive status and error clear */ cc2538_reg_t ECR; /**< UART receive status and error clear */ @@ -38,6 +42,9 @@ typedef struct { cc2538_reg_t RESERVED1[4]; /**< Reserved addresses */ + /** + * @brief Flag register + */ union { cc2538_reg_t FR; /**< UART Flag Register */ struct { @@ -57,6 +64,9 @@ typedef struct { cc2538_reg_t IBRD; /**< UART Integer Baud-Rate Divisor */ cc2538_reg_t FBRD; /**< UART Fractional Baud-Rate Divisor */ + /** + * @brief Line control register + */ union { cc2538_reg_t LCRH; /**< UART Line Control Register */ struct { @@ -71,6 +81,9 @@ typedef struct { } LCRHbits; } cc2538_uart_lcrh; + /** + * @brief Control register + */ union { cc2538_reg_t CTL; /**< UART Control */ struct { @@ -91,6 +104,9 @@ typedef struct { } CTLbits; } cc2538_uart_ctl; + /** + * @brief Interrupt FIFO level select register + */ union { cc2538_reg_t IFLS; /**< UART interrupt FIFO Level Select */ struct { @@ -100,6 +116,9 @@ typedef struct { } IFLSbits; } cc2538_uart_ifls; + /** + * @brief Interrupt mask register + */ union { cc2538_reg_t IM; /**< UART Interrupt Mask */ struct { @@ -122,6 +141,9 @@ typedef struct { cc2538_reg_t RIS; /**< UART Raw Interrupt Status */ + /** + * @brief Masked interrupt status register + */ union { cc2538_reg_t MIS; /**< UART Masked Interrupt Status */ struct {