cpu/nrf53: add initial support

Signed-off-by: Dylan Laduranty <dylan.laduranty@mesotic.com>

cpu/nrf53/Makefile

@@ -0,0 +1,7 @@
+# define the module that is build
+MODULE = cpu
+
+# add a list of subdirectories, that should also be build
+DIRS = periph $(RIOTCPU)/cortexm_common $(RIOTCPU)/nrf5x_common vectors
+
+include $(RIOTBASE)/Makefile.base

cpu/nrf53/Makefile.dep

@@ -0,0 +1,4 @@
+USEMODULE += nrf53_vectors
+
+include $(RIOTCPU)/nrf5x_common/Makefile.dep
+include $(RIOTCPU)/cortexm_common/Makefile.dep

cpu/nrf53/Makefile.features

@@ -0,0 +1,4 @@
+CPU_CORE = cortex-m33
+CPU_FAM  = nrf53
+
+include $(RIOTCPU)/nrf5x_common/Makefile.features

cpu/nrf53/Makefile.include

@@ -0,0 +1,8 @@
+ROM_LEN ?= 0x100000
+RAM_LEN ?= 0x80000
+
+PROGRAMMER ?= jlink
+JLINK_DEVICE = NRF5340_XXAA_APP
+
+include $(RIOTCPU)/nrf5x_common/Makefile.include
+include $(RIOTMAKE)/arch/cortexm.inc.mk

cpu/nrf53/cpu.c

@@ -0,0 +1,63 @@
+/*
+ * Copyright (C) 2023 Mesotic SAS
+ *
+ * This file is subject to the terms and conditions of the GNU Lesser
+ * General Public License v2.1. See the file LICENSE in the top level
+ * directory for more details.
+ */
+
+/**
+ * @ingroup     cpu_nrf53
+ * @{
+ *
+ * @file
+ * @brief       Implementation of the CPU initialization
+ *
+ * @author      Dylan Laduranty <dylan.laduranty@mesotic.com>
+ *
+ * @}
+ */
+
+#include "assert.h"
+#include "cpu.h"
+#include "kernel_init.h"
+#include "nrf_clock.h"
+#include "periph_conf.h"
+#include "periph/init.h"
+#include "stdio_base.h"
+#include "board.h"
+
+/**
+ * @brief   Initialize the CPU, set IRQ priorities
+ */
+void cpu_init(void)
+{
+    /* initialize hf clock */
+static_assert((CLOCK_CORECLOCK == MHZ(128)) || CLOCK_CORECLOCK == MHZ(64));
+#if (CLOCK_CORECLOCK == MHZ(128))
+    NRF_CLOCK_S->HFCLKCTRL = CLOCK_HFCLKCTRL_HCLK_Div1;
+#else
+    NRF_CLOCK_S->HFCLKCTRL = CLOCK_HFCLKCTRL_HCLK_Div2;
+#endif
+    /* Selects external 32MHz oscillator as clock source*/
+#if (CLOCK_HFCLK == CLOCK_HFCLKSRC_SRC_HFINT)
+    NRF_CLOCK_S->HFCLKSRC = CLOCK_HFCLKSRC_SRC_HFINT;
+#else
+    NRF_CLOCK_S->HFCLKSRC = CLOCK_HFCLKSRC_SRC_HFXO;
+#endif
+    NRF_CLOCK_S->TASKS_HFCLKSTART = 1;
+
+    /* Enable instruction cache */
+    NRF_CACHE_S->ENABLE = CACHE_ENABLE_ENABLE_Enabled;
+    /* For now, disable the unused network core */
+    NRF_RESET_S->NETWORK.FORCEOFF = 1;
+
+    /* call cortexm default initialization */
+    cortexm_init();
+
+    /* initialize stdio prior to periph_init() to allow use of DEBUG() there */
+    early_init();
+
+    /* trigger static peripheral initialization */
+    periph_init();
+}

cpu/nrf53/include/cpu_conf.h

@@ -0,0 +1,60 @@
+/*
+ * Copyright (C) 2023 Mesotic SAS
+ *
+ * This file is subject to the terms and conditions of the GNU Lesser
+ * General Public License v2.1. See the file LICENSE in the top level
+ * directory for more details.
+ */
+
+/**
+ * @defgroup        cpu_nrf53 Nordic nRF53 MCU
+ * @ingroup         cpu
+ * @brief           Nordic nRF53 family of CPUs
+ * @{
+ *
+ * @file
+ * @brief       nRF53 specific CPU configuration
+ *
+ * @author      Dylan Laduranty <dylan.laduranty@mesotic.com>
+ *
+ */
+
+#ifndef CPU_CONF_H
+#define CPU_CONF_H
+
+#ifdef CPU_MODEL_NRF5340_APP
+#include "vendor/nrf5340_application.h"
+#include "vendor/nrf5340_application_bitfields.h"
+#include "vendor/nrf5340_application_peripherals.h"
+#elif defined(CPU_MODEL_NRF5340_NET)
+#include "vendor/nrf5340_network.h"
+#include "vendor/nrf5340_network_bitfields.h"
+#include "vendor/nrf5340_network_peripherals.h"
+#else
+#error "The CPU_MODEL of your board is currently not supported"
+#endif
+
+#include "cpu_conf_common.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @name    ARM Cortex-M specific CPU configuration
+ * @{
+ */
+#define CPU_DEFAULT_IRQ_PRIO            (1U)    /**< Default ARM IRQ priority */
+
+#ifdef CPU_MODEL_NRF5340_APP
+#define CPU_FLASH_BASE                  (0x00000000) /**< ROM Base Address */
+#define CPU_IRQ_NUMOF                   (69U)   /**< nRF53 specific IRQ count */
+#endif /* def CPU_MODEL_NRF5340_APP */
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* CPU_CONF_H */
+/** @} */

cpu/nrf53/include/periph_cpu.h

@@ -0,0 +1,58 @@
+/*
+ * Copyright (C) 2023 Mesotic SAS
+ *
+ * This file is subject to the terms and conditions of the GNU Lesser
+ * General Public License v2.1. See the file LICENSE in the top level
+ * directory for more details.
+ */
+
+/**
+ * @ingroup         cpu_nrf53
+ * @{
+ *
+ * @file
+ * @brief           nRF5340 specific definitions for handling peripherals
+ *
+ * @author          Dylan Laduranty <dylan.laduranty@mesotic.com>
+ */
+
+#ifndef PERIPH_CPU_H
+#define PERIPH_CPU_H
+
+#include "periph_cpu_common.h"
+#include "macros/units.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifndef DOXYGEN
+/**
+ * @brief Wrapper to fix differences between nRF families vendor files
+  */
+#define UART_BAUDRATE_BAUDRATE_Baud1200 UARTE_BAUDRATE_BAUDRATE_Baud1200
+#define UART_BAUDRATE_BAUDRATE_Baud2400 UARTE_BAUDRATE_BAUDRATE_Baud2400
+#define UART_BAUDRATE_BAUDRATE_Baud4800 UARTE_BAUDRATE_BAUDRATE_Baud4800
+#define UART_BAUDRATE_BAUDRATE_Baud9600 UARTE_BAUDRATE_BAUDRATE_Baud9600
+#define UART_BAUDRATE_BAUDRATE_Baud14400 UARTE_BAUDRATE_BAUDRATE_Baud14400
+#define UART_BAUDRATE_BAUDRATE_Baud19200 UARTE_BAUDRATE_BAUDRATE_Baud19200
+#define UART_BAUDRATE_BAUDRATE_Baud28800 UARTE_BAUDRATE_BAUDRATE_Baud28800
+#define UART_BAUDRATE_BAUDRATE_Baud31250 UARTE_BAUDRATE_BAUDRATE_Baud31250
+#define UART_BAUDRATE_BAUDRATE_Baud38400 UARTE_BAUDRATE_BAUDRATE_Baud38400
+#define UART_BAUDRATE_BAUDRATE_Baud56000 UARTE_BAUDRATE_BAUDRATE_Baud56000
+#define UART_BAUDRATE_BAUDRATE_Baud57600 UARTE_BAUDRATE_BAUDRATE_Baud57600
+#define UART_BAUDRATE_BAUDRATE_Baud76800 UARTE_BAUDRATE_BAUDRATE_Baud76800
+#define UART_BAUDRATE_BAUDRATE_Baud115200 UARTE_BAUDRATE_BAUDRATE_Baud115200
+#define UART_BAUDRATE_BAUDRATE_Baud230400 UARTE_BAUDRATE_BAUDRATE_Baud230400
+#define UART_BAUDRATE_BAUDRATE_Baud250000 UARTE_BAUDRATE_BAUDRATE_Baud250000
+#define UART_BAUDRATE_BAUDRATE_Baud460800 UARTE_BAUDRATE_BAUDRATE_Baud460800
+#define UART_BAUDRATE_BAUDRATE_Baud921600 UARTE_BAUDRATE_BAUDRATE_Baud921600
+#define UART_BAUDRATE_BAUDRATE_Baud1M UARTE_BAUDRATE_BAUDRATE_Baud1M
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PERIPH_CPU_H */
+/** @} */

cpu/nrf53/include/vendor/nrf5340_application_name_change.h

@@ -0,0 +1,63 @@
+/*
+
+Copyright (c) 2010 - 2023, Nordic Semiconductor ASA All rights reserved.
+
+SPDX-License-Identifier: BSD-3-Clause
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+1. Redistributions of source code must retain the above copyright notice, this
+   list of conditions and the following disclaimer.
+
+2. Redistributions in binary form must reproduce the above copyright
+   notice, this list of conditions and the following disclaimer in the
+   documentation and/or other materials provided with the distribution.
+
+3. Neither the name of Nordic Semiconductor ASA nor the names of its
+   contributors may be used to endorse or promote products derived from this
+   software without specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE
+ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
+LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGE.
+
+*/
+
+#ifndef NRF5340_APPLICATION_NAME_CHANGE_H
+#define NRF5340_APPLICATION_NAME_CHANGE_H
+
+/*lint ++flb "Enter library region */
+
+/* This file is given to prevent your SW from not compiling with the updates made to nrf5340_application.h and
+ * nrf5340_application_bitfields.h. The macros defined in this file were available previously. Do not use these
+ * macros on purpose. Use the ones defined in nrf5340_application.h and nrf5340_application_bitfields.h instead.
+ */
+
+/* The serial box interrupt ISRs were renamed. Adding old names as macros. */
+#define SPIM0_SPIS0_TWIM0_TWIS0_UARTE0_IRQHandler       SERIAL0_IRQHandler
+#define SPIM0_SPIS0_TWIM0_TWIS0_UARTE0_IRQn             SERIAL0_IRQn
+#define SPIM1_SPIS1_TWIM1_TWIS1_UARTE1_IRQHandler       SERIAL1_IRQHandler
+#define SPIM1_SPIS1_TWIM1_TWIS1_UARTE1_IRQn             SERIAL1_IRQn
+#define SPIM2_SPIS2_TWIM2_TWIS2_UARTE2_IRQHandler       SERIAL2_IRQHandler
+#define SPIM2_SPIS2_TWIM2_TWIS2_UARTE2_IRQn             SERIAL2_IRQn
+#define SPIM3_SPIS3_TWIM3_TWIS3_UARTE3_IRQHandler       SERIAL3_IRQHandler
+#define SPIM3_SPIS3_TWIM3_TWIS3_UARTE3_IRQn             SERIAL3_IRQn
+
+/* DPPI */
+#define DPPI_PRESENT   DPPIC_PRESENT
+#define DPPI_COUNT     DPPIC_COUNT
+#define DPPI_CH_NUM    DPPIC_CH_NUM
+#define DPPI_GROUP_NUM DPPIC_GROUP_NUM
+
+/*lint --flb "Leave library region" */
+
+#endif /* NRF5340_APPLICATION_NAME_CHANGE_H */

cpu/nrf53/include/vendor/nrf5340_application_peripherals.h

@@ -0,0 +1,310 @@
+/*
+
+Copyright (c) 2010 - 2023, Nordic Semiconductor ASA All rights reserved.
+
+SPDX-License-Identifier: BSD-3-Clause
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+1. Redistributions of source code must retain the above copyright notice, this
+   list of conditions and the following disclaimer.
+
+2. Redistributions in binary form must reproduce the above copyright
+   notice, this list of conditions and the following disclaimer in the
+   documentation and/or other materials provided with the distribution.
+
+3. Neither the name of Nordic Semiconductor ASA nor the names of its
+   contributors may be used to endorse or promote products derived from this
+   software without specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE
+ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
+LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGE.
+
+*/
+
+#ifndef _NRF5340_PERIPHERALS_H
+#define _NRF5340_PERIPHERALS_H
+
+
+/* Clock Peripheral */
+#define CLOCK_PRESENT
+#define CLOCK_COUNT 1
+
+#define CLOCK_FEATURE_HFCLK_DIVIDE_PRESENT
+
+/* Power Peripheral */
+#define POWER_PRESENT
+#define POWER_COUNT 1
+
+/* Non-Volatile Memory Controller */
+#define NVMC_PRESENT
+#define NVMC_COUNT 1
+
+/* NVM instruction  and data cache */
+#define CACHE_PRESENT
+#define CACHE_COUNT 1
+
+/* Memory Protection Unit */
+#define MPU_REGION_NUM 8
+
+/* Regulators Peripheral */
+#define REGULATORS_PRESENT
+#define REGULATORS_COUNT 1
+
+#define REGULATORS_FEATURE_VDDH_PRESENT
+
+/* USB Regulator Peripheral */
+#define USBREG_PRESENT
+#define USBREG_COUNT 1
+
+/* Volatile Memory Controller Peripheral */
+#define VMC_PRESENT
+#define VMC_COUNT 1
+
+#define VMC_FEATURE_RAM_REGISTERS_PRESENT
+#define VMC_FEATURE_RAM_REGISTERS_COUNT 8
+
+/* Floating Point Unit */
+#define FPU_PRESENT
+#define FPU_COUNT 1
+
+/* Systick timer */
+#define SYSTICK_PRESENT
+#define SYSTICK_COUNT 1
+
+/* Inter-Processor Communication */
+#define IPC_PRESENT
+#define IPC_COUNT 1
+
+#define IPC_CH_NUM 16
+#define IPC_CONF_NUM 16
+#define IPC_GPMEM_NUM 2
+
+/* GPIO */
+#define GPIO_PRESENT
+#define GPIO_COUNT 2
+
+#define P0_PIN_NUM 32
+#define P1_PIN_NUM 16
+
+#define P0_FEATURE_PINS_PRESENT 0xFFFFFFFFUL
+#define P1_FEATURE_PINS_PRESENT 0x0000FFFFUL
+
+/* NFC Tag */
+#define NFCT_PRESENT
+#define NFCT_COUNT 1
+
+#define NFCT_EASYDMA_MAXCNT_SIZE 9
+
+/* Distributed Peripheral to Peripheral Interconnect */
+#define DPPIC_PRESENT
+#define DPPIC_COUNT 1
+
+#define DPPIC_CH_NUM 32
+#define DPPIC_GROUP_NUM 6
+
+/* Event Generator Unit */
+#define EGU_PRESENT
+#define EGU_COUNT 6
+
+#define EGU0_CH_NUM 16
+#define EGU1_CH_NUM 16
+#define EGU2_CH_NUM 16
+#define EGU3_CH_NUM 16
+#define EGU4_CH_NUM 16
+#define EGU5_CH_NUM 16
+
+/* Timer/Counter */
+#define TIMER_PRESENT
+#define TIMER_COUNT 3
+
+#define TIMER0_MAX_SIZE 32
+#define TIMER1_MAX_SIZE 32
+#define TIMER2_MAX_SIZE 32
+
+#define TIMER0_CC_NUM 6
+#define TIMER1_CC_NUM 6
+#define TIMER2_CC_NUM 6
+
+/* Real Time Counter */
+#define RTC_PRESENT
+#define RTC_COUNT 2
+
+#define RTC0_CC_NUM 4
+#define RTC1_CC_NUM 4
+
+/* Watchdog Timer */
+#define WDT_PRESENT
+#define WDT_COUNT 2
+
+/* Serial Peripheral Interface Master with DMA */
+#define SPIM_PRESENT
+#define SPIM_COUNT 5
+
+#define SPIM0_MAX_DATARATE  8
+#define SPIM1_MAX_DATARATE  8
+#define SPIM2_MAX_DATARATE  8
+#define SPIM3_MAX_DATARATE  8
+#define SPIM4_MAX_DATARATE  32
+
+#define SPIM0_FEATURE_HARDWARE_CSN_PRESENT  0
+#define SPIM1_FEATURE_HARDWARE_CSN_PRESENT  0
+#define SPIM2_FEATURE_HARDWARE_CSN_PRESENT  0
+#define SPIM3_FEATURE_HARDWARE_CSN_PRESENT  0
+#define SPIM4_FEATURE_HARDWARE_CSN_PRESENT  1
+
+#define SPIM0_FEATURE_DCX_PRESENT  0
+#define SPIM1_FEATURE_DCX_PRESENT  0
+#define SPIM2_FEATURE_DCX_PRESENT  0
+#define SPIM3_FEATURE_DCX_PRESENT  0
+#define SPIM4_FEATURE_DCX_PRESENT  1
+
+#define SPIM0_FEATURE_RXDELAY_PRESENT  0
+#define SPIM1_FEATURE_RXDELAY_PRESENT  0
+#define SPIM2_FEATURE_RXDELAY_PRESENT  0
+#define SPIM3_FEATURE_RXDELAY_PRESENT  0
+#define SPIM4_FEATURE_RXDELAY_PRESENT  1
+
+#define SPIM0_EASYDMA_MAXCNT_SIZE 16
+#define SPIM1_EASYDMA_MAXCNT_SIZE 16
+#define SPIM2_EASYDMA_MAXCNT_SIZE 16
+#define SPIM3_EASYDMA_MAXCNT_SIZE 16
+#define SPIM4_EASYDMA_MAXCNT_SIZE 16
+
+/* Serial Peripheral Interface Slave with DMA*/
+#define SPIS_PRESENT
+#define SPIS_COUNT 4
+
+#define SPIS0_EASYDMA_MAXCNT_SIZE 16
+#define SPIS1_EASYDMA_MAXCNT_SIZE 16
+#define SPIS2_EASYDMA_MAXCNT_SIZE 16
+#define SPIS3_EASYDMA_MAXCNT_SIZE 16
+
+/* Two Wire Interface Master with DMA */
+#define TWIM_PRESENT
+#define TWIM_COUNT 4
+
+#define TWIM0_EASYDMA_MAXCNT_SIZE 16
+#define TWIM1_EASYDMA_MAXCNT_SIZE 16
+#define TWIM2_EASYDMA_MAXCNT_SIZE 16
+#define TWIM3_EASYDMA_MAXCNT_SIZE 16
+
+/* Two Wire Interface Slave with DMA */
+#define TWIS_PRESENT
+#define TWIS_COUNT 4
+
+#define TWIS0_EASYDMA_MAXCNT_SIZE 16
+#define TWIS1_EASYDMA_MAXCNT_SIZE 16
+#define TWIS2_EASYDMA_MAXCNT_SIZE 16
+#define TWIS3_EASYDMA_MAXCNT_SIZE 16
+
+/* Universal Asynchronous Receiver-Transmitter with DMA */
+#define UARTE_PRESENT
+#define UARTE_COUNT 4
+
+#define UARTE0_EASYDMA_MAXCNT_SIZE 16
+#define UARTE1_EASYDMA_MAXCNT_SIZE 16
+#define UARTE2_EASYDMA_MAXCNT_SIZE 16
+#define UARTE3_EASYDMA_MAXCNT_SIZE 16
+
+/* Quadrature Decoder */
+#define QDEC_PRESENT
+#define QDEC_COUNT 2
+
+/* Successive Approximation Analog to Digital Converter */
+#define SAADC_PRESENT
+#define SAADC_COUNT 1
+
+#define SAADC_CH_NUM 8
+#define SAADC_EASYDMA_MAXCNT_SIZE 15
+
+/* GPIO Tasks and Events */
+#define GPIOTE_PRESENT
+#define GPIOTE_COUNT 2
+
+#define GPIOTE_CH_NUM 8
+
+#define GPIOTE_FEATURE_SET_PRESENT
+#define GPIOTE_FEATURE_CLR_PRESENT
+
+/* Low Power Comparator */
+#define LPCOMP_PRESENT
+#define LPCOMP_COUNT 1
+
+#define LPCOMP_REFSEL_RESOLUTION 16
+
+#define LPCOMP_FEATURE_HYST_PRESENT
+
+/* Comparator */
+#define COMP_PRESENT
+#define COMP_COUNT 1
+
+/* Pulse Width Modulator */
+#define PWM_PRESENT
+#define PWM_COUNT 4
+
+#define PWM0_CH_NUM 4
+#define PWM1_CH_NUM 4
+#define PWM2_CH_NUM 4
+#define PWM3_CH_NUM 4
+
+#define PWM0_EASYDMA_MAXCNT_SIZE 15
+#define PWM1_EASYDMA_MAXCNT_SIZE 15
+#define PWM2_EASYDMA_MAXCNT_SIZE 15
+#define PWM3_EASYDMA_MAXCNT_SIZE 15
+
+/* ARM TrustZone Cryptocell 310 */
+#define CRYPTOCELL_PRESENT
+#define CRYPTOCELL_COUNT 1
+
+/* Quad SPI */
+#define QSPI_PRESENT
+#define QSPI_COUNT 1
+
+#define QSPI_EASYDMA_MAXCNT_SIZE 20
+
+/* Mutex*/
+#define MUTEX_PRESENT
+#define MUTEX_COUNT 1
+
+/* Key management Unit */
+#define KMU_PRESENT
+#define KMU_COUNT 1
+
+/* Pulse density modulation */
+#define PDM_PRESENT
+#define PDM_COUNT 1
+
+/* Secure Peripheral Unit */
+#define SPU_PRESENT
+#define SPU_COUNT 1
+
+#define SPU_RAMREGION_SIZE 0x2000ul
+
+/* Inter-IC Sound Interface */
+#define I2S_PRESENT
+#define I2S_COUNT 1
+
+#define I2S_EASYDMA_MAXCNT_SIZE 14
+
+/* Universal Serial Bus Device */
+#define USBD_PRESENT
+#define USBD_COUNT 1
+
+#define USBD_EASYDMA_MAXCNT_SIZE 7
+
+/* Oscillators */
+#define OSCILLATORS_PRESENT
+#define OSCILLATORS_COUNT 1
+
+#endif      // _NRF5340_PERIPHERALS_H

cpu/nrf53/include/vendor/nrf5340_network_name_change.h

@@ -0,0 +1,57 @@
+/*
+
+Copyright (c) 2010 - 2023, Nordic Semiconductor ASA All rights reserved.
+
+SPDX-License-Identifier: BSD-3-Clause
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+1. Redistributions of source code must retain the above copyright notice, this
+   list of conditions and the following disclaimer.
+
+2. Redistributions in binary form must reproduce the above copyright
+   notice, this list of conditions and the following disclaimer in the
+   documentation and/or other materials provided with the distribution.
+
+3. Neither the name of Nordic Semiconductor ASA nor the names of its
+   contributors may be used to endorse or promote products derived from this
+   software without specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE
+ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
+LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGE.
+
+*/
+
+#ifndef NRF5340_NETWORK_NAME_CHANGE_H
+#define NRF5340_NETWORK_NAME_CHANGE_H
+
+/*lint ++flb "Enter library region */
+
+/* This file is given to prevent your SW from not compiling with the updates made to nrf5340_network.h and
+ * nrf5340_network_bitfields.h. The macros defined in this file were available previously. Do not use these
+ * macros on purpose. Use the ones defined in nrf5340_network.h and nrf5340_network_bitfields.h instead.
+ */
+ 
+/* The serial box interrupt ISRs were renamed. Adding old names as macros. */
+#define SPIM0_SPIS0_TWIM0_TWIS0_UARTE0_IRQHandler          SERIAL0_IRQHandler
+#define SPIM0_SPIS0_TWIM0_TWIS0_UARTE0_IRQn                SERIAL0_IRQn
+ 
+ /* DPPI */
+#define DPPI_PRESENT   DPPIC_PRESENT
+#define DPPI_COUNT     DPPIC_COUNT
+#define DPPI_CH_NUM    DPPIC_CH_NUM
+#define DPPI_GROUP_NUM DPPIC_GROUP_NUM
+ 
+ /*lint --flb "Leave library region" */
+
+#endif /* NRF5340_NETWORK_NAME_CHANGE_H */

cpu/nrf53/include/vendor/nrf5340_network_peripherals.h

@@ -0,0 +1,213 @@
+/*
+
+Copyright (c) 2010 - 2023, Nordic Semiconductor ASA All rights reserved.
+
+SPDX-License-Identifier: BSD-3-Clause
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+1. Redistributions of source code must retain the above copyright notice, this
+   list of conditions and the following disclaimer.
+
+2. Redistributions in binary form must reproduce the above copyright
+   notice, this list of conditions and the following disclaimer in the
+   documentation and/or other materials provided with the distribution.
+
+3. Neither the name of Nordic Semiconductor ASA nor the names of its
+   contributors may be used to endorse or promote products derived from this
+   software without specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE
+ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
+LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGE.
+
+*/
+
+#ifndef _NRF5340_NETWORK_PERIPHERALS_H
+#define _NRF5340_NETWORK_PERIPHERALS_H
+
+
+/* Clock Peripheral */
+#define CLOCK_PRESENT
+#define CLOCK_COUNT 1
+
+/* Power Peripheral */
+#define POWER_PRESENT
+#define POWER_COUNT 1
+
+/* Non-Volatile Memory Controller */
+#define NVMC_PRESENT
+#define NVMC_COUNT 1
+
+#define NVMC_FEATURE_CACHE_PRESENT
+
+/* Voltage request peripheral */
+#define VREQCTRL_PRESENT
+#define VREQCTRL_COUNT 1
+
+/* Volatile Memory Controller Peripheral */
+#define VMC_PRESENT
+#define VMC_COUNT 1
+
+#define VMC_FEATURE_RAM_REGISTERS_PRESENT
+#define VMC_FEATURE_RAM_REGISTERS_COUNT 4
+
+/* Systick timer */
+#define SYSTICK_PRESENT
+#define SYSTICK_COUNT 1
+
+/* Inter-Processor Communication */
+#define IPC_PRESENT
+#define IPC_COUNT 1
+
+#define IPC_CH_NUM 16
+#define IPC_CONF_NUM 16
+#define IPC_GPMEM_NUM 2
+
+/* GPIO */
+#define GPIO_PRESENT
+#define GPIO_COUNT 2
+
+#define P0_PIN_NUM 32
+#define P1_PIN_NUM 16
+
+#define P0_FEATURE_PINS_PRESENT 0xFFFFFFFFUL
+#define P1_FEATURE_PINS_PRESENT 0x0000FFFFUL
+
+
+/* ACL */
+#define ACL_PRESENT
+#define ACL_REGIONS_COUNT 8
+
+/* Radio */
+#define RADIO_PRESENT
+#define RADIO_COUNT 1
+
+#define RADIO_EASYDMA_MAXCNT_SIZE 9
+#define RADIO_FEATURE_IEEE_802_15_4_PRESENT
+
+#define RADIO_TXPOWER_TXPOWER_Max RADIO_TXPOWER_TXPOWER_0dBm
+
+/* Accelerated Address Resolver */
+#define AAR_PRESENT
+#define AAR_COUNT 1
+
+#define AAR_MAX_IRK_NUM 16
+
+/* AES Electronic CodeBook mode encryption */
+#define ECB_PRESENT
+#define ECB_COUNT 1
+
+/* AES CCM mode encryption */
+#define CCM_PRESENT
+#define CCM_COUNT 1
+
+/* Distributed Peripheral to Peripheral Interconnect */
+#define DPPIC_PRESENT
+#define DPPIC_COUNT 1
+
+#define DPPIC_CH_NUM 32
+#define DPPIC_GROUP_NUM 6
+
+/* Event Generator Unit */
+#define EGU_PRESENT
+#define EGU_COUNT 1
+
+#define EGU0_CH_NUM 16
+
+/* Timer/Counter */
+#define TIMER_PRESENT
+#define TIMER_COUNT 3
+
+#define TIMER0_MAX_SIZE 32
+#define TIMER1_MAX_SIZE 32
+#define TIMER2_MAX_SIZE 32
+
+#define TIMER0_CC_NUM 8
+#define TIMER1_CC_NUM 8
+#define TIMER2_CC_NUM 8
+
+/* Real Time Counter */
+#define RTC_PRESENT
+#define RTC_COUNT 2
+
+#define RTC0_CC_NUM 4
+#define RTC1_CC_NUM 4
+
+/* RNG */
+#define RNG_PRESENT
+#define RNG_COUNT 1
+
+/* Watchdog Timer */
+#define WDT_PRESENT
+#define WDT_COUNT 1
+
+/* Temperature Sensor */
+#define TEMP_PRESENT
+#define TEMP_COUNT 1
+
+/* Universal Asynchronous Receiver-Transmitter with DMA */
+#define UARTE_PRESENT
+#define UARTE_COUNT 1
+
+#define UARTE0_EASYDMA_MAXCNT_SIZE 16
+
+/* Serial Peripheral Interface Master with DMA */
+#define SPIM_PRESENT
+#define SPIM_COUNT 1
+
+#define SPIM0_MAX_DATARATE  8
+
+#define SPIM0_FEATURE_HARDWARE_CSN_PRESENT  0
+
+#define SPIM0_FEATURE_DCX_PRESENT  0
+
+#define SPIM0_FEATURE_RXDELAY_PRESENT  0
+
+#define SPIM0_EASYDMA_MAXCNT_SIZE 16
+
+/* Serial Peripheral Interface Slave with DMA*/
+#define SPIS_PRESENT
+#define SPIS_COUNT 1
+
+#define SPIS0_EASYDMA_MAXCNT_SIZE 16
+
+/* Two Wire Interface Master with DMA */
+#define TWIM_PRESENT
+#define TWIM_COUNT 1
+
+#define TWIM0_EASYDMA_MAXCNT_SIZE 16
+
+/* Two Wire Interface Slave with DMA */
+#define TWIS_PRESENT
+#define TWIS_COUNT 1
+
+#define TWIS0_EASYDMA_MAXCNT_SIZE 16
+
+/* GPIO Tasks and Events */
+#define GPIOTE_PRESENT
+#define GPIOTE_COUNT 1
+
+#define GPIOTE_CH_NUM 8
+
+#define GPIOTE_FEATURE_SET_PRESENT
+#define GPIOTE_FEATURE_CLR_PRESENT
+
+/* Software Interrupts */
+#define SWI_PRESENT
+#define SWI_COUNT 4
+
+/* Mutex*/
+#define MUTEX_PRESENT
+#define MUTEX_COUNT 1
+
+#endif      // _NRF5340_NETWORK_PERIPHERALS_H

cpu/nrf53/periph/Makefile

@@ -0,0 +1 @@
+include $(RIOTMAKE)/periph.mk

cpu/nrf53/vectors/Kconfig

@@ -0,0 +1,11 @@
+# Copyright (c) 2023 Mesotic SAS
+#
+# This file is subject to the terms and conditions of the GNU Lesser
+# General Public License v2.1. See the file LICENSE in the top level
+# directory for more details.
+#
+
+config MODULE_NRF53_VECTORS
+    bool
+    depends on TEST_KCONFIG
+    default y

cpu/nrf53/vectors/Makefile

@@ -0,0 +1,11 @@
+MODULE = nrf53_vectors
+
+NO_AUTO_SRC = 1
+
+SRC_FILE = vectors_$(CPU_MODEL).c
+
+SRCS += $(SRC_FILE)
+# (file triggers compiler bug. see #5775)
+SRC_NOLTO += $(SRC_FILE)
+
+include $(RIOTBASE)/Makefile.base

cpu/nrf53/vectors/vectors_nrf5340_app.c

@@ -0,0 +1,118 @@
+/*
+ * Copyright (C) 2023 Mesotic SAS
+ *
+ * This file is subject to the terms and conditions of the GNU Lesser
+ * General Public License v2.1. See the file LICENSE in the top level
+ * directory for more details.
+ */
+
+/**
+ * @ingroup     cpu_nrf53
+ * @{
+ *
+ * @file
+ * @brief       nRF5340 interrupt vector definitions
+ *
+ * @author      Dylan Laduranty <dylan.laduranty@mesotic.com>
+ *
+ * @}
+ */
+
+#include <stdint.h>
+
+#include "cpu.h"
+#include "vectors_cortexm.h"
+
+/* define a local dummy handler as it needs to be in the same compilation unit
+ * as the alias definition */
+void dummy_handler(void) {
+    dummy_handler_default();
+}
+
+/* nRF5340 specific interrupt vectors */
+WEAK_DEFAULT void isr_fpu(void);
+WEAK_DEFAULT void isr_cache(void);
+WEAK_DEFAULT void isr_spu(void);
+WEAK_DEFAULT void isr_clock_power(void);
+WEAK_DEFAULT void isr_serial0(void);
+WEAK_DEFAULT void isr_serial1(void);
+WEAK_DEFAULT void isr_spim4(void);
+WEAK_DEFAULT void isr_serial2(void);
+WEAK_DEFAULT void isr_serial3(void);
+WEAK_DEFAULT void isr_gpiote0(void);
+WEAK_DEFAULT void isr_saadc(void);
+WEAK_DEFAULT void isr_timer0(void);
+WEAK_DEFAULT void isr_timer1(void);
+WEAK_DEFAULT void isr_timer2(void);
+WEAK_DEFAULT void isr_rtc0(void);
+WEAK_DEFAULT void isr_rtc1(void);
+WEAK_DEFAULT void isr_wdt0(void);
+WEAK_DEFAULT void isr_wdt1(void);
+WEAK_DEFAULT void isr_comp_ltcomp(void);
+WEAK_DEFAULT void isr_egu0(void);
+WEAK_DEFAULT void isr_egu1(void);
+WEAK_DEFAULT void isr_egu2(void);
+WEAK_DEFAULT void isr_egu3(void);
+WEAK_DEFAULT void isr_egu4(void);
+WEAK_DEFAULT void isr_egu5(void);
+WEAK_DEFAULT void isr_pwm0(void);
+WEAK_DEFAULT void isr_pwm1(void);
+WEAK_DEFAULT void isr_pwm2(void);
+WEAK_DEFAULT void isr_pwm3(void);
+WEAK_DEFAULT void isr_pdm0(void);
+WEAK_DEFAULT void isr_i2s0(void);
+WEAK_DEFAULT void isr_ipc(void);
+WEAK_DEFAULT void isr_qspi(void);
+WEAK_DEFAULT void isr_nfct(void);
+WEAK_DEFAULT void isr_gpiote1(void);
+WEAK_DEFAULT void isr_qdec0(void);
+WEAK_DEFAULT void isr_qdec1(void);
+WEAK_DEFAULT void isr_usbd(void);
+WEAK_DEFAULT void isr_usb_regulator(void);
+WEAK_DEFAULT void isr_kmu(void);
+WEAK_DEFAULT void isr_cryptocell(void);
+
+/* CPU specific interrupt vector table */
+ISR_VECTOR(1) const isr_t vector_cpu[CPU_IRQ_NUMOF] = {
+ [0] = isr_fpu,
+ [1] = isr_cache,
+ [3] = isr_spu,
+ [5] = isr_clock_power,
+ [8] = isr_serial0,
+ [9] = isr_serial1,
+ [10] = isr_spim4,
+ [11] = isr_serial2,
+ [12] = isr_serial3,
+ [13] = isr_gpiote0,
+ [14] = isr_saadc,
+ [15] = isr_timer0,
+ [16] = isr_timer1,
+ [17] = isr_timer2,
+ [20] = isr_rtc0,
+ [21] = isr_rtc1,
+ [24] = isr_wdt0,
+ [25] = isr_wdt1,
+ [26] = isr_comp_ltcomp,
+ [27] = isr_egu0,
+ [28] = isr_egu1,
+ [29] = isr_egu2,
+ [30] = isr_egu3,
+ [31] = isr_egu4,
+ [32] = isr_egu5,
+ [33] = isr_pwm0,
+ [34] = isr_pwm1,
+ [35] = isr_pwm2,
+ [36] = isr_pwm3,
+ [38] = isr_pdm0,
+ [40] = isr_i2s0,
+ [42] = isr_ipc,
+ [43] = isr_qspi,
+ [45] = isr_nfct,
+ [47] = isr_gpiote1,
+ [51] = isr_qdec0,
+ [52] = isr_qdec1,
+ [54] = isr_usbd,
+ [55] = isr_usb_regulator,
+ [57] = isr_kmu,
+ [68] = isr_cryptocell
+};

cpu/nrf5x_common/Makefile.features

@@ -1,14 +1,18 @@
 # Put defined MCU peripherals here (in alphabetical order)
+FEATURES_PROVIDED += periph_gpio periph_gpio_irq
+FEATURES_PROVIDED += periph_timer_periodic
+FEATURES_PROVIDED += periph_uart_modecfg
+
+ifeq (,$(filter nrf5340_app,$(CPU_MODEL)))
 FEATURES_PROVIDED += periph_cpuid
 FEATURES_PROVIDED += periph_flashpage
 FEATURES_PROVIDED += periph_flashpage_in_address_space
 FEATURES_PROVIDED += periph_flashpage_pagewise
-FEATURES_PROVIDED += periph_gpio periph_gpio_irq
 FEATURES_PROVIDED += periph_gpio_ll periph_gpio_ll_irq periph_gpio_ll_irq_unmask
-FEATURES_PROVIDED += periph_timer_periodic
-FEATURES_PROVIDED += periph_uart_modecfg
+endif
 
-ifneq (nrf9160,$(CPU_MODEL))
+# nRF9160/nRF5340 don't support these drivers right now
+ifeq (,$(filter nrf9160 nrf5340_app,$(CPU_MODEL)))
   FEATURES_PROVIDED += periph_hwrng
   FEATURES_PROVIDED += periph_rtt_overflow
   FEATURES_PROVIDED += periph_temperature

cpu/nrf5x_common/clock.c

@@ -31,7 +31,7 @@
 #error "Clock init: CLOCK_LFCLK is not defined by your board!"
 #endif
 
-/* Add compatibility wrapper defines for nRF9160 */
+/* Add compatibility wrapper defines for nRF families with Cortex-M33 core */
 #ifdef NRF_CLOCK_S
 #define NRF_CLOCK NRF_CLOCK_S
 #endif

cpu/nrf5x_common/include/periph_cpu_common.h

@@ -69,6 +69,18 @@ extern "C" {
  * PWM.PSEL.OUT where it is used in sign-extended form to get a UINT32_MAX */
 #define GPIO_UNDEF          (UINT8_MAX)
 
+/**
+ * @brief   Wrapper around GPIOTE ISR
+ *
+ * @note    nRF53 has two GPIOTE instances available on Application Core
+ *          but we always use the first one.
+ */
+#ifdef NRF_GPIOTE0_S
+#define ISR_GPIOTE isr_gpiote0
+#else
+#define ISR_GPIOTE isr_gpiote
+#endif
+
 /**
  * @brief   Generate GPIO mode bitfields
  *
@@ -209,7 +221,7 @@ typedef struct {
  * @brief   Override SPI mode values
  * @{
  */
-#ifndef CPU_FAM_NRF9160
+#if !defined(CPU_FAM_NRF9160) && !defined(CPU_FAM_NRF53)
 #define HAVE_SPI_MODE_T
 typedef enum {
     SPI_MODE_0 = 0,                                             /**< CPOL=0, CPHA=0 */

cpu/nrf5x_common/periph/gpio.c

@@ -43,6 +43,10 @@
 #define NRF_P0 NRF_P0_S
 #endif
 
+#ifdef NRF_P1_S
+#define NRF_P1 NRF_P1_S
+#endif
+
 #ifdef NRF_GPIOTE0_S
 #define NRF_GPIOTE NRF_GPIOTE0_S
 #define GPIOTE_IRQn GPIOTE0_IRQn
@@ -227,7 +231,7 @@ void gpio_irq_disable(gpio_t pin)
     }
 }
 
-void isr_gpiote(void)
+void ISR_GPIOTE(void)
 {
     for (unsigned int i = 0; i < _gpiote_next_index; ++i) {
         if (NRF_GPIOTE->EVENTS_IN[i] == 1) {

cpu/nrf5x_common/periph/pm.c

@@ -30,7 +30,7 @@
 /* TODO: implement proper pm_off for nRF9160 */
 void pm_off(void)
 {
-#ifndef CPU_FAM_NRF9160
+#if (!defined(CPU_FAM_NRF9160) && !defined(CPU_FAM_NRF53))
 #ifdef CPU_FAM_NRF51
     NRF_POWER->RAMON = 0;
 #else