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Merge pull request #8441 from fjmolinas/nucleo-l452

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boards/nucleo-l452: initial support
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Alexandre Abadie 2018-03-05 19:01:09 +01:00 committed by GitHub
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8 changed files with 16341 additions and 8 deletions
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4
boards/nucleo-l452re/Makefile Normal file
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@ -0,0 +1,4 @@
MODULE = board
DIRS = $(RIOTBOARD)/common/nucleo
include $(RIOTBASE)/Makefile.base

1
boards/nucleo-l452re/Makefile.dep Normal file
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include $(RIOTBOARD)/common/nucleo/Makefile.dep

16
boards/nucleo-l452re/Makefile.features Normal file
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# Put defined MCU peripherals here (in alphabetical order)
FEATURES_PROVIDED += periph_gpio
FEATURES_PROVIDED += periph_pwm
FEATURES_PROVIDED += periph_rtc
FEATURES_PROVIDED += periph_rtt
FEATURES_PROVIDED += periph_spi
FEATURES_PROVIDED += periph_timer
FEATURES_PROVIDED += periph_uart
# load the common Makefile.features for Nucleo boards
include $(RIOTBOARD)/common/nucleo64/Makefile.features
# The board MPU family (used for grouping by the CI system)
FEATURES_MCU_GROUP = cortex_m4_2
-include $(RIOTCPU)/stm32l4/Makefile.features

6
boards/nucleo-l452re/Makefile.include Normal file
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## the cpu to build for
export CPU = stm32l4
export CPU_MODEL = stm32l452re
# load the common Makefile.include for Nucleo boards
include $(RIOTBOARD)/common/nucleo64/Makefile.include

232
boards/nucleo-l452re/include/periph_conf.h Normal file
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@ -0,0 +1,232 @@
/*
* Copyright (C) 2017 Freie Universität Berlin
* 2017 Inria
* 2017 HAW-Hamburg
* 2018 Fundacion Inria Chile
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @defgroup boards_nucleo-l452re STM32 Nucleo-L452RE
* @ingroup boards_common_nucleo64
* @brief Support for the STM32 Nucleo-L452RE
* @{
*
* @file
* @brief Peripheral MCU configuration for the nucleo-l452re board
*
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
* @author Alexandre Abadie <alexandre.abadie@inria.fr>
* @author Michel Rottleuthner <michel.rottleuthner@haw-hamburg.de>
* @author Francisco Molina <francisco.molina@inria.cl>
*/
#ifndef PERIPH_CONF_H
#define PERIPH_CONF_H
#include "periph_cpu.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @name Clock system configuration
* @{
*/
/* 0: no external high speed crystal available
* else: actual crystal frequency [in Hz] */
#define CLOCK_HSE (0)
#ifndef CLOCK_LSE
/* 0: no external low speed crystal available,
* 1: external crystal available (always 32.768kHz) */
#define CLOCK_LSE (0)
#endif
/* 0: enable MSI only if HSE isn't available
* 1: always enable MSI (e.g. if USB or RNG is used)*/
#define CLOCK_MSI_ENABLE (1)
#ifndef CLOCK_MSI_LSE_PLL
/* 0: disable Hardware auto calibration with LSE
* 1: enable Hardware auto calibration with LSE (PLL-mode)
* Same as with CLOCK_LSE above this defaults to 0 because LSE is
* mandatory for MSI/LSE-trimming to work */
#define CLOCK_MSI_LSE_PLL (0)
#endif
/* give the target core clock (HCLK) frequency [in Hz], maximum: 80MHz */
#define CLOCK_CORECLOCK (80000000U)
/* PLL configuration: make sure your values are legit!
*
* compute by: CORECLOCK = (((PLL_IN / M) * N) / R)
* with:
* PLL_IN: input clock, HSE or MSI @ 48MHz
* M: pre-divider, allowed range: [1:8]
* N: multiplier, allowed range: [8:86]
* R: post-divider, allowed range: [2,4,6,8]
*
* Also the following constraints need to be met:
* (PLL_IN / M) -> [4MHz:16MHz]
* (PLL_IN / M) * N -> [64MHz:344MHz]
* CORECLOCK -> 80MHz MAX!
*/
#define CLOCK_PLL_M (6)
#define CLOCK_PLL_N (20)
#define CLOCK_PLL_R (2)
/* peripheral clock setup */
#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV4
#define CLOCK_APB1 (CLOCK_CORECLOCK / 4)
#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV2
#define CLOCK_APB2 (CLOCK_CORECLOCK / 2)
/** @} */
/**
* @name Timer configuration
* @{
*/
static const timer_conf_t timer_config[] = {
{
.dev = TIM2,
.max = 0xffffffff,
.rcc_mask = RCC_APB1ENR1_TIM2EN,
.bus = APB1,
.irqn = TIM2_IRQn
}
};
#define TIMER_0_ISR isr_tim2
#define TIMER_NUMOF (sizeof(timer_config) / sizeof(timer_config[0]))
/** @} */
/**
* @name UART configuration
* @{
*/
static const uart_conf_t uart_config[] = {
{
.dev = USART2,
.rcc_mask = RCC_APB1ENR1_USART2EN,
.rx_pin = GPIO_PIN(PORT_A, 3),
.tx_pin = GPIO_PIN(PORT_A, 2),
.rx_af = GPIO_AF7,
.tx_af = GPIO_AF7,
.bus = APB1,
.irqn = USART2_IRQn,
},
{
.dev = USART3,
.rcc_mask = RCC_APB1ENR1_USART3EN,
.rx_pin = GPIO_PIN(PORT_C, 11),
.tx_pin = GPIO_PIN(PORT_C, 10),
.rx_af = GPIO_AF7,
.tx_af = GPIO_AF7,
.bus = APB1,
.irqn = USART3_IRQn,
}
};
#define UART_0_ISR (isr_usart2)
#define UART_1_ISR (isr_usart3)
#define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0]))
/** @} */
/**
* @name PWM configuration
* @{
*/
static const pwm_conf_t pwm_config[] = {
{
.dev = TIM3,
.rcc_mask = RCC_APB1ENR1_TIM3EN,
.chan = { { .pin = GPIO_PIN(PORT_B, 4), .cc_chan = 0 },
{ .pin = GPIO_PIN(PORT_C, 7), .cc_chan = 1},
{ .pin = GPIO_PIN(PORT_C, 8), .cc_chan = 2},
{ .pin = GPIO_PIN(PORT_C, 9), .cc_chan = 3} },
.af = GPIO_AF2,
.bus = APB1
},
};
#define PWM_NUMOF (sizeof(pwm_config) / sizeof(pwm_config[0]))
/** @} */
/**
* @name SPI configuration
*
* @note The spi_divtable is auto-generated from
* `cpu/stm32_common/dist/spi_divtable/spi_divtable.c`
* @{
*/
static const uint8_t spi_divtable[2][5] = {
{ /* for APB1 @ 20000000Hz */
7, /* -> 78125Hz */
5, /* -> 312500Hz */
3, /* -> 1250000Hz */
1, /* -> 5000000Hz */
0 /* -> 10000000Hz */
},
{ /* for APB2 @ 40000000Hz */
7, /* -> 156250Hz */
6, /* -> 312500Hz */
4, /* -> 1250000Hz */
2, /* -> 5000000Hz */
1 /* -> 10000000Hz */
}
};
static const spi_conf_t spi_config[] = {
{
.dev = SPI1,
.mosi_pin = GPIO_PIN(PORT_A, 7),
.miso_pin = GPIO_PIN(PORT_A, 6),
.sclk_pin = GPIO_PIN(PORT_A, 5),
.cs_pin = GPIO_UNDEF,
.af = GPIO_AF5,
.rccmask = RCC_APB2ENR_SPI1EN,
.apbbus = APB2
},
};
#define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
/** @} */
/**
* @name ADC configuration
* @{
*/
#define ADC_NUMOF (0)
/** @} */
/**
* @name RTT configuration
*
* On the STM32Lx platforms, we always utilize the LPTIM1.
* @{
*/
#define RTT_NUMOF (1)
#define RTT_FREQUENCY (1024U) /* 32768 / 2^n */
#define RTT_MAX_VALUE (0x0000ffff) /* 16-bit timer */
/** @} */
/**
* @name RTC configuration
* @{
*/
#define RTC_NUMOF (1)
/** @} */
#ifdef __cplusplus
}
#endif
#endif /* PERIPH_CONF_H */
/** @} */

2
cpu/stm32l4/include/cpu_conf.h
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@ -31,6 +31,8 @@
#include "vendor/stm32l475xx.h"
#elif defined(CPU_MODEL_STM32L432KC)
#include "vendor/stm32l432xx.h"
#elif defined(CPU_MODEL_STM32L452RE)
#include "vendor/stm32l452xx.h"
#endif
#ifdef __cplusplus

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cpu/stm32l4/include/vendor/stm32l452xx.h vendored Normal file
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23
cpu/stm32l4/vectors.c
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@ -146,7 +146,6 @@ ISR_VECTOR(1) const isr_t vector_cpu[CPU_IRQ_NUMOF] = {
[RTC_Alarm_IRQn ] = isr_rtc_alarm, /* [41] RTC Alarm (A and B) through EXTI Line Interrupt */
[SPI3_IRQn ] = isr_spi3, /* [51] SPI3 global Interrupt */
[TIM6_DAC_IRQn ] = isr_tim6_dac, /* [54] TIM6 global and DAC1&2 underrun error interrupts */
[TIM7_IRQn ] = isr_tim7, /* [55] TIM7 global interrupt */
[DMA2_Channel1_IRQn ] = isr_dma2_channel1, /* [56] DMA2 Channel 1 global Interrupt */
[DMA2_Channel2_IRQn ] = isr_dma2_channel2, /* [57] DMA2 Channel 2 global Interrupt */
[DMA2_Channel3_IRQn ] = isr_dma2_channel3, /* [58] DMA2 Channel 3 global Interrupt */
@ -162,7 +161,6 @@ ISR_VECTOR(1) const isr_t vector_cpu[CPU_IRQ_NUMOF] = {
[I2C3_EV_IRQn ] = isr_i2c3_ev, /* [72] I2C3 event interrupt */
[I2C3_ER_IRQn ] = isr_i2c3_er, /* [73] I2C3 error interrupt */
[SAI1_IRQn ] = isr_sai1, /* [74] Serial Audio Interface 1 global interrupt */
[SWPMI1_IRQn ] = isr_swpmi1, /* [76] Serial Wire Interface 1 global interrupt */
[TSC_IRQn ] = isr_tsc, /* [77] Touch Sense Controller global interrupt */
[RNG_IRQn ] = isr_rng, /* [80] RNG global interrupt */
[FPU_IRQn ] = isr_fpu, /* [81] FPU global interrupt */
@ -172,15 +170,23 @@ ISR_VECTOR(1) const isr_t vector_cpu[CPU_IRQ_NUMOF] = {
[TIM1_TRG_COM_IRQn ] = isr_tim1_trg_com, /* [26] TIM1 Trigger and Commutation Interrupt */
[USB_IRQn ] = isr_usb, /* [67] USB event Interrupt */
[CRS_IRQn ] = isr_crs, /* [82] CRS global interrupt */
#elif defined(CPU_MODEL_STM32L476RG) || defined(CPU_MODEL_STM32L475VG)
#endif
#if defined(CPU_MODEL_STM32L476RG) || defined(CPU_MODEL_STM32L475VG) || \
defined(CPU_MODEL_STM32L452RE)
[ADC1_2_IRQn ] = isr_adc1_2, /* [18] ADC1, ADC2 SAR global Interrupts */
[TIM1_TRG_COM_TIM17_IRQn ] = isr_tim1_trg_com_tim17, /* [26] TIM1 Trigger and Commutation Interrupt and TIM17 global interrupt */
[TIM3_IRQn ] = isr_tim3, /* [29] TIM3 global Interrupt */
[TIM4_IRQn ] = isr_tim4, /* [30] TIM4 global Interrupt */
[I2C2_EV_IRQn ] = isr_i2c2_ev, /* [33] I2C2 Event Interrupt */
[I2C2_ER_IRQn ] = isr_i2c2_er, /* [34] I2C2 Error Interrupt */
[SPI2_IRQn ] = isr_spi2, /* [36] SPI2 global Interrupt */
[USART3_IRQn ] = isr_usart3, /* [39] USART3 global Interrupt */
[SDMMC1_IRQn ] = isr_sdmmc1, /* [49] SDMMC1 global Interrupt */
[UART4_IRQn ] = isr_uart4, /* [52] UART4 global Interrupt */
[DFSDM1_FLT0_IRQn ] = isr_dfsdm1_flt0, /* [61] DFSDM1 Filter 0 global Interrupt */
[DFSDM1_FLT1_IRQn ] = isr_dfsdm1_flt1, /* [62] DFSDM1 Filter 1 global Interrupt */
#endif
#if defined(CPU_MODEL_STM32L476RG) || defined(CPU_MODEL_STM32L475VG)
[TIM4_IRQn ] = isr_tim4, /* [30] TIM4 global Interrupt */
[DFSDM1_FLT3_IRQn ] = isr_dfsdm1_flt3, /* [42] DFSDM1 Filter 3 global Interrupt */
[TIM8_BRK_IRQn ] = isr_tim8_brk, /* [43] TIM8 Break Interrupt */
[TIM8_UP_IRQn ] = isr_tim8_up, /* [44] TIM8 Update Interrupt */
@ -188,16 +194,17 @@ ISR_VECTOR(1) const isr_t vector_cpu[CPU_IRQ_NUMOF] = {
[TIM8_CC_IRQn ] = isr_tim8_cc, /* [46] TIM8 Capture Compare Interrupt */
[ADC3_IRQn ] = isr_adc3, /* [47] ADC3 global Interrupt */
[FMC_IRQn ] = isr_fmc, /* [48] FMC global Interrupt */
[SDMMC1_IRQn ] = isr_sdmmc1, /* [49] SDMMC1 global Interrupt */
[TIM5_IRQn ] = isr_tim5, /* [50] TIM5 global Interrupt */
[UART4_IRQn ] = isr_uart4, /* [52] UART4 global Interrupt */
[UART5_IRQn ] = isr_uart5, /* [53] UART5 global Interrupt */
[DFSDM1_FLT0_IRQn ] = isr_dfsdm1_flt0, /* [61] DFSDM1 Filter 0 global Interrupt */
[DFSDM1_FLT1_IRQn ] = isr_dfsdm1_flt1, /* [62] DFSDM1 Filter 1 global Interrupt */
[DFSDM1_FLT2_IRQn ] = isr_dfsdm1_flt2, /* [63] DFSDM1 Filter 2 global Interrupt */
[OTG_FS_IRQn ] = isr_otg_fs, /* [67] USB OTG FS global Interrupt */
[SAI2_IRQn ] = isr_sai2, /* [75] Serial Audio Interface 2 global interrupt */
#endif
#if defined(CPU_MODEL_STM32L432KC) || defined(CPU_MODEL_STM32L476RG) || \
defined(CPU_MODEL_STM32L475VG)
[TIM7_IRQn ] = isr_tim7, /* [55] TIM7 global interrupt */
[SWPMI1_IRQn ] = isr_swpmi1, /* [76] Serial Wire Interface 1 global interrupt */
#endif
#if defined(CPU_MODEL_STM32L476RG)
[LCD_IRQn ] = isr_lcd, /* [78] LCD global interrupt */
#endif