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boards/nucleo-f411: initial support
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3
boards/nucleo-f411/Makefile
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3
boards/nucleo-f411/Makefile
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MODULE = board
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include $(RIOTBASE)/Makefile.base
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1
boards/nucleo-f411/Makefile.dep
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1
boards/nucleo-f411/Makefile.dep
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include $(RIOTBOARD)/nucleo-common/Makefile.dep
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14
boards/nucleo-f411/Makefile.features
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14
boards/nucleo-f411/Makefile.features
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# Put defined MCU peripherals here (in alphabetical order)
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FEATURES_PROVIDED += periph_cpuid
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FEATURES_PROVIDED += periph_i2c
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FEATURES_PROVIDED += periph_gpio
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FEATURES_PROVIDED += periph_pwm
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FEATURES_PROVIDED += periph_spi
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FEATURES_PROVIDED += periph_timer
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FEATURES_PROVIDED += periph_uart
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# Various other features (if any)
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FEATURES_PROVIDED += cpp
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# The board MPU family (used for grouping by the CI system)
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FEATURES_MCU_GROUP = cortex_m4_3
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6
boards/nucleo-f411/Makefile.include
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6
boards/nucleo-f411/Makefile.include
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# define the cpu used by the nucleo-f411 board
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export CPU = stm32f4
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export CPU_MODEL = stm32f411re
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# load the common Makefile.include for Nucleo boards
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include $(RIOTBOARD)/nucleo-common/Makefile.include
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31
boards/nucleo-f411/board.c
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31
boards/nucleo-f411/board.c
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/*
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* Copyright (C) 2016 Inria
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup boards_nucleo-f411
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* @{
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*
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* @file
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* @brief Board specific implementations for the nucleo-f411 board
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*
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* @author Alexandre Abadie <alexandre.abadie@inria.fr>
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*
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* @}
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*/
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#include "board.h"
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#include "periph/gpio.h"
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void board_init(void)
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{
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/* initialize the CPU */
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cpu_init();
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/* initialize the boards LEDs */
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gpio_init(LED0_PIN, GPIO_OUT);
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}
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1
boards/nucleo-f411/dist/openocd.cfg
vendored
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1
boards/nucleo-f411/dist/openocd.cfg
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source [find board/st_nucleo_f4.cfg]
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45
boards/nucleo-f411/include/board.h
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45
boards/nucleo-f411/include/board.h
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/*
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* Copyright (C) 2016 Inria
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*
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* This file is subject to the terms and conditions of the GNU Lesser General
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* Public License v2.1. See the file LICENSE in the top level directory for more
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* details.
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*/
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/**
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* @defgroup boards_nucleo-f411 Nucleo-F411
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* @ingroup boards
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* @brief Board specific files for the nucleo-f411 board
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* @{
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*
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* @file
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* @brief Board specific definitions for the nucleo-f411 board
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*
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* @author Alexandre Abadie <alexandre.abadie@inria.fr>
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*/
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#ifndef BOARD_H_
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#define BOARD_H_
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#include "board_common.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @name xtimer configuration
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* @{
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*/
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#define XTIMER_DEV TIMER_DEV(0)
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#define XTIMER_CHAN (0)
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#define XTIMER_OVERHEAD (6)
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#define XTIMER_BACKOFF (5)
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/** @} */
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#ifdef __cplusplus
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}
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#endif
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#endif /* BOARD_H_ */
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/** @} */
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248
boards/nucleo-f411/include/periph_conf.h
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248
boards/nucleo-f411/include/periph_conf.h
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/*
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* Copyright (C) 2016 Inria
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup boards_nucleo-f411
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* @{
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*
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* @file
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* @name Peripheral MCU configuration for the nucleo-f411 board
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*
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* @author Alexandre Abadie <alexandre.abadie@inria.fr>
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*/
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#ifndef PERIPH_CONF_H_
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#define PERIPH_CONF_H_
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#include "periph_cpu.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @name Clock system configuration
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* @{
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*/
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#define CLOCK_HSE (8000000U) /* external oscillator */
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#define CLOCK_CORECLOCK (100000000U) /* desired core clock frequency */
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/* the actual PLL values are automatically generated */
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#define CLOCK_PLL_M (CLOCK_HSE / 1000000)
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#define CLOCK_PLL_N ((CLOCK_CORECLOCK / 1000000) * 2)
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#define CLOCK_PLL_P (2U)
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#define CLOCK_PLL_Q (CLOCK_PLL_N / 48)
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#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
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#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2
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#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1
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#define CLOCK_FLASH_LATENCY FLASH_ACR_LATENCY_5WS
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/* bus clocks for simplified peripheral initialization, UPDATE MANUALLY! */
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#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
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#define CLOCK_APB1 (CLOCK_CORECLOCK / 2)
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#define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
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/** @} */
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/**
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* @name Timer configuration
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* @{
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*/
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static const timer_conf_t timer_config[] = {
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{
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.dev = TIM5,
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.max = 0xffffffff,
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.rcc_mask = RCC_APB1ENR_TIM5EN,
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.bus = APB1,
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.irqn = TIM5_IRQn
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}
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};
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#define TIMER_0_ISR isr_tim5
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#define TIMER_1_ISR isr_tim4
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#define TIMER_NUMOF (sizeof(timer_config) / sizeof(timer_config[0]))
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/** @} */
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/**
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* @brief UART configuration
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* @{
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*/
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static const uart_conf_t uart_config[] = {
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{
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.dev = USART2,
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.rcc_mask = RCC_APB1ENR_USART2EN,
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.rx_pin = GPIO_PIN(PORT_A,3),
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.tx_pin = GPIO_PIN(PORT_A,2),
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.rx_af = GPIO_AF7,
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.tx_af = GPIO_AF7,
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.bus = APB1,
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.irqn = USART2_IRQn,
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#ifdef UART_USE_DMA
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.dma_stream = 6,
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.dma_chan = 4
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#endif
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},
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{
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.dev = USART1,
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.rcc_mask = RCC_APB2ENR_USART1EN,
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.rx_pin = GPIO_PIN(PORT_A, 10),
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.tx_pin = GPIO_PIN(PORT_A, 9),
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.rx_af = GPIO_AF7,
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.tx_af = GPIO_AF7,
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.bus = APB2,
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.irqn = USART1_IRQn,
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#ifdef UART_USE_DMA
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.dma_stream = 6,
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.dma_chan = 3
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#endif
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},
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{
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.dev = USART6,
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.rcc_mask = RCC_APB2ENR_USART6EN,
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.rx_pin = GPIO_PIN(PORT_A, 12),
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.tx_pin = GPIO_PIN(PORT_A, 11),
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.rx_af = GPIO_AF8,
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.tx_af = GPIO_AF8,
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.bus = APB2,
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.irqn = USART6_IRQn,
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#ifdef UART_USE_DMA
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.dma_stream = 6,
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.dma_chan = 2
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#endif
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}
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};
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/* assign ISR vector names */
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#define UART_0_ISR isr_usart2
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#define UART_0_DMA_ISR isr_dma1_stream6
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#define UART_1_ISR isr_usart1
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#define UART_1_DMA_ISR isr_dma1_stream6
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#define UART_2_ISR isr_usart6
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#define UART_2_DMA_ISR isr_dma1_stream6
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/* deduct number of defined UART interfaces */
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#define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0]))
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/** @} */
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/** @brief PWM configuration
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* @{
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*/
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static const pwm_conf_t pwm_config[] = {
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{
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.dev = TIM2,
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.rcc_mask = RCC_APB1ENR_TIM2EN,
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.chan = { { .pin = GPIO_PIN(PORT_A, 15) , .cc_chan = 0 },
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{ .pin = GPIO_PIN(PORT_B, 3) /* D3 */, .cc_chan = 1 },
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{ .pin = GPIO_PIN(PORT_B, 10) /* D6 */, .cc_chan = 2 },
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{ .pin = GPIO_UNDEF, .cc_chan = 0 } },
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.af = GPIO_AF1,
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.bus = APB1
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},
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{
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.dev = TIM3,
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.rcc_mask = RCC_APB1ENR_TIM3EN,
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.chan = { { .pin = GPIO_PIN(PORT_B, 4) /* D5 */, .cc_chan = 0 },
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{ .pin = GPIO_PIN(PORT_C, 7) /* D9 */, .cc_chan = 1 },
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{ .pin = GPIO_PIN(PORT_C, 8), .cc_chan = 2 },
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{ .pin = GPIO_PIN(PORT_C, 9), .cc_chan = 3 } },
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.af = GPIO_AF2,
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.bus = APB1
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},
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};
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#define PWM_NUMOF (sizeof(pwm_config) / sizeof(pwm_config[0]))
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/** @} */
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/**
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* @brief SPI configuration
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*
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* @note The spi_divtable is auto-generated from
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* `cpu/stm32_common/dist/spi_divtable/spi_divtable.c`
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* @{
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*/
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static const uint8_t spi_divtable[2][5] = {
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{ /* for APB1 @ 50000000Hz */
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7, /* -> 195312Hz */
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6, /* -> 390625Hz */
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5, /* -> 781250Hz */
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2, /* -> 6250000Hz */
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1 /* -> 12500000Hz */
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},
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{ /* for APB2 @ 100000000Hz */
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7, /* -> 390625Hz */
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7, /* -> 390625Hz */
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6, /* -> 781250Hz */
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3, /* -> 6250000Hz */
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2 /* -> 12500000Hz */
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}
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};
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static const spi_conf_t spi_config[] = {
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{
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.dev = SPI1,
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.mosi_pin = GPIO_PIN(PORT_A, 7),
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.miso_pin = GPIO_PIN(PORT_A, 6),
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.sclk_pin = GPIO_PIN(PORT_A, 5),
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.cs_pin = GPIO_PIN(PORT_A, 4),
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.af = GPIO_AF5,
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.rccmask = RCC_APB2ENR_SPI1EN,
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.apbbus = APB2
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}
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};
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#define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
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/** @} */
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/**
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* @name I2C configuration
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* @{
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*/
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#define I2C_NUMOF (1U)
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#define I2C_0_EN 1
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#define I2C_IRQ_PRIO 1
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#define I2C_APBCLK (42000000U)
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/* I2C 0 device configuration */
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#define I2C_0_DEV I2C1
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#define I2C_0_CLKEN() (RCC->APB1ENR |= RCC_APB1ENR_I2C1EN)
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#define I2C_0_CLKDIS() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
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#define I2C_0_EVT_IRQ I2C1_EV_IRQn
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#define I2C_0_EVT_ISR isr_i2c1_ev
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#define I2C_0_ERR_IRQ I2C1_ER_IRQn
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#define I2C_0_ERR_ISR isr_i2c1_er
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/* I2C 0 pin configuration */
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#define I2C_0_SCL_PORT GPIOB
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#define I2C_0_SCL_PIN 8
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#define I2C_0_SCL_AF 4
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#define I2C_0_SCL_CLKEN() (RCC->AHB1ENR |= RCC_AHB1ENR_GPIOBEN)
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#define I2C_0_SDA_PORT GPIOB
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#define I2C_0_SDA_PIN 9
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#define I2C_0_SDA_AF 4
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#define I2C_0_SDA_CLKEN() (RCC->AHB1ENR |= RCC_AHB1ENR_GPIOBEN)
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/** @} */
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/**
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* @brief ADC configuration
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* @{
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*/
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#define ADC_NUMOF (0)
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/** @} */
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/**
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* @brief DAC configuration
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* @{
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*/
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#define DAC_NUMOF (0)
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/** @} */
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#ifdef __cplusplus
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}
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#endif
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#endif /* PERIPH_CONF_H_ */
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/** @} */
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