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cpu/cortexm: move CPU_ARCH/FAM to Makefile.features

This commit is contained in:
Alexandre Abadie 2020-01-30 09:49:47 +01:00
parent 9866cdd411
commit d7c0102115
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GPG Key ID: 1C919A403CAE1405
44 changed files with 60 additions and 57 deletions

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@ -1,3 +1,5 @@
CPU_ARCH = cortex-m3
FEATURES_PROVIDED += periph_cpuid
FEATURES_PROVIDED += periph_gpio periph_gpio_irq
FEATURES_PROVIDED += periph_hwrng

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@ -1,3 +1 @@
CPU_ARCH = cortex-m3
include $(RIOTMAKE)/arch/cortexm.inc.mk

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@ -1 +1,3 @@
CPU_ARCH = cortex-m3
-include $(RIOTCPU)/cc26xx_cc13xx/Makefile.features

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CPU_ARCH = cortex-m3
CPU_VARIANT = x0
VECTORS_O = $(BINDIR)/cc26xx_cc13xx/vectors.o

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@ -1 +1,3 @@
CPU_ARCH = cortex-m4f
-include $(RIOTCPU)/cc26xx_cc13xx/Makefile.features

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@ -1,4 +1,3 @@
CPU_ARCH = cortex-m4f
CPU_VARIANT = x2
VECTORS_O = $(BINDIR)/cc26xx_cc13xx/vectors.o

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@ -1,3 +1,5 @@
CPU_ARCH = cortex-m4f
FEATURES_PROVIDED += periph_cpuid
FEATURES_PROVIDED += periph_gpio periph_gpio_irq

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@ -1,3 +1 @@
CPU_ARCH = cortex-m4f
include $(RIOTMAKE)/arch/cortexm.inc.mk

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@ -1 +1,3 @@
CPU_ARCH = cortex-m4f
-include $(RIOTCPU)/cortexm_common/Makefile.features

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@ -1,5 +1,3 @@
CPU_ARCH = cortex-m4f
include $(RIOTMAKE)/arch/cortexm.inc.mk
include $(RIOTCPU)/stellaris_common/Makefile.include

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@ -1,5 +1,7 @@
CPU_ARCH = cortex-m3
# This CPU only implements one CPU_MODEL with the same name
CPU_MODEL = lpc1768
FEATURES_PROVIDED += periph_cpuid
FEATURES_PROVIDED += periph_pm

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@ -1,3 +1 @@
CPU_ARCH = cortex-m3
include $(RIOTMAKE)/arch/cortexm.inc.mk

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@ -1 +1,4 @@
CPU_ARCH = cortex-m0
CPU_FAM = nrf51
-include $(RIOTCPU)/nrf5x_common/Makefile.features

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@ -1,5 +1,2 @@
CPU_ARCH = cortex-m0
CPU_FAM = nrf51
include $(RIOTCPU)/nrf5x_common/Makefile.include
include $(RIOTMAKE)/arch/cortexm.inc.mk

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@ -1,3 +1,6 @@
CPU_ARCH = cortex-m4f
CPU_FAM = nrf52
# The ADC does not depend on any board configuration, so always available
FEATURES_PROVIDED += periph_adc

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@ -1,6 +1,3 @@
CPU_ARCH = cortex-m4f
CPU_FAM = nrf52
# Slot size is determined by "((total_flash_size - RIOTBOOT_LEN) / 2)".
# If RIOTBOOT_LEN uses an uneven number of flashpages, the remainder of the
# flash cannot be divided by two slots while staying FLASHPAGE_SIZE aligned.

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@ -1,3 +1,6 @@
CPU_ARCH = cortex-m3
CPU_FAM = sam3
FEATURES_PROVIDED += periph_cpuid
FEATURES_PROVIDED += periph_hwrng

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@ -1,5 +1,2 @@
CPU_ARCH = cortex-m3
CPU_FAM = sam3
include $(RIOTCPU)/sam_common/Makefile.include
include $(RIOTMAKE)/arch/cortexm.inc.mk

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@ -1,3 +1,6 @@
CPU_ARCH = cortex-m0plus
CPU_FAM = samd21
FEATURES_PROVIDED += puf_sram
-include $(RIOTCPU)/sam0_common/Makefile.features

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@ -1,6 +1,3 @@
CPU_ARCH = cortex-m0plus
CPU_FAM = samd21
ifneq (,$(filter samd21%a,$(CPU_MODEL)))
CFLAGS += -DCPU_SAMD21A
endif

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@ -1,3 +1,6 @@
CPU_ARCH = cortex-m4f
CPU_FAM = samd5x
FEATURES_PROVIDED += periph_hwrng
FEATURES_PROVIDED += backup_ram

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@ -1,6 +1,3 @@
CPU_ARCH = cortex-m4f
CPU_FAM = samd5x
ifneq (,$(filter samd51%,$(CPU_MODEL)))
CFLAGS += -DCPU_SAMD51
endif

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@ -1,3 +1,6 @@
CPU_ARCH = cortex-m23
CPU_FAM = saml1x
FEATURES_PROVIDED += periph_hwrng
include $(RIOTCPU)/sam0_common/Makefile.features

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@ -1,5 +1,3 @@
CPU_ARCH = cortex-m23
ifneq (,$(filter saml10%,$(CPU_MODEL)))
CFLAGS += -DCPU_SAML10
endif

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@ -1,3 +1,6 @@
CPU_ARCH = cortex-m0plus
CPU_FAM = saml21
# The SAMR30 line of MCUs does not contain a TRNG
BOARDS_WITHOUT_HWRNG += samr30-xpro

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@ -1,6 +1,3 @@
CPU_ARCH = cortex-m0plus
CPU_FAM = saml21
ifneq (,$(filter saml21%a,$(CPU_MODEL)))
CFLAGS += -DCPU_SAML21A
endif

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@ -1,3 +1,6 @@
CPU_ARCH = cortex-m0
CPU_FAM = stm32f0
ifeq (,$(filter nucleo-f031k6,$(BOARD)))
FEATURES_PROVIDED += periph_flashpage
FEATURES_PROVIDED += periph_flashpage_raw

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@ -1,5 +1,2 @@
CPU_ARCH = cortex-m0
CPU_FAM = stm32f0
include $(RIOTCPU)/stm32_common/Makefile.include
include $(RIOTMAKE)/arch/cortexm.inc.mk

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@ -1,3 +1,6 @@
CPU_ARCH = cortex-m3
CPU_FAM = stm32f1
FEATURES_PROVIDED += periph_flashpage
FEATURES_PROVIDED += periph_flashpage_raw
FEATURES_PROVIDED += periph_rtc

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@ -1,5 +1,2 @@
CPU_ARCH = cortex-m3
CPU_FAM = stm32f1
include $(RIOTCPU)/stm32_common/Makefile.include
include $(RIOTMAKE)/arch/cortexm.inc.mk

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@ -1,3 +1,6 @@
CPU_ARCH = cortex-m3
CPU_FAM = stm32f2
FEATURES_PROVIDED += periph_hwrng
-include $(RIOTCPU)/stm32_common/Makefile.features

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@ -1,6 +1,3 @@
CPU_ARCH = cortex-m3
CPU_FAM = stm32f2
# STM32F2 uses sectors instead of pages, where the minimum sector length is 16KB
# (the first sector), therefore RIOTBOOT_LEN must be 16KB to cover a whole sector.
RIOTBOOT_LEN ?= 0x4000

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@ -1,3 +1,6 @@
CPU_ARCH = cortex-m4f
CPU_FAM = stm32f3
FEATURES_PROVIDED += periph_flashpage
FEATURES_PROVIDED += periph_flashpage_raw

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@ -1,5 +1,2 @@
CPU_ARCH = cortex-m4f
CPU_FAM = stm32f3
include $(RIOTCPU)/stm32_common/Makefile.include
include $(RIOTMAKE)/arch/cortexm.inc.mk

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@ -1,3 +1,6 @@
CPU_ARCH = cortex-m4f
CPU_FAM = stm32f4
FEATURES_PROVIDED += periph_hwrng
# the granularity of provided feature definition for STMs is currently by CPU

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@ -1,6 +1,3 @@
CPU_ARCH = cortex-m4f
CPU_FAM = stm32f4
# STM32F4 uses sectors instead of pages, where the minimum sector length is 16KB
# (the first sector), therefore RIOTBOOT_LEN must be 16KB to cover a whole sector.
RIOTBOOT_LEN ?= 0x4000

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CPU_ARCH = cortex-m7
CPU_FAM = stm32f7
FEATURES_PROVIDED += periph_hwrng
-include $(RIOTCPU)/stm32_common/Makefile.features

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@ -1,6 +1,3 @@
CPU_ARCH = cortex-m7
CPU_FAM = stm32f7
# STM32F7 uses sectors instead of pages, where the minimum sector length is 16KB or
# 32kB (the first sector), depending on the CPU_MODEL. Therefore RIOTBOOT_LEN must
# be 16KB or 32kB to cover a whole sector.

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CPU_ARCH = cortex-m0plus
CPU_FAM = stm32l0
FEATURES_PROVIDED += periph_eeprom
FEATURES_PROVIDED += periph_flashpage
FEATURES_PROVIDED += periph_flashpage_raw

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@ -1,5 +1,2 @@
CPU_ARCH = cortex-m0plus
CPU_FAM = stm32l0
include $(RIOTCPU)/stm32_common/Makefile.include
include $(RIOTMAKE)/arch/cortexm.inc.mk

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CPU_ARCH = cortex-m3
CPU_FAM = stm32l1
FEATURES_PROVIDED += periph_eeprom
FEATURES_PROVIDED += periph_flashpage
FEATURES_PROVIDED += periph_flashpage_raw

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@ -1,5 +1,2 @@
CPU_ARCH = cortex-m3
CPU_FAM = stm32l1
include $(RIOTCPU)/stm32_common/Makefile.include
include $(RIOTMAKE)/arch/cortexm.inc.mk

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CPU_ARCH = cortex-m4f
CPU_FAM = stm32l4
FEATURES_PROVIDED += periph_flashpage
FEATURES_PROVIDED += periph_flashpage_raw
FEATURES_PROVIDED += periph_hwrng

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@ -1,6 +1,3 @@
CPU_ARCH = cortex-m4f
CPU_FAM = stm32l4
# "The Vector table must be naturally aligned to a power of two whose alignment
# value is greater than or equal to number of Exceptions supported x 4"
# CPU_IRQ_NUMOFF for stm32l4 boards is < 91+16 so (107*4 bytes = 428 bytes ~= 0x200)