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cpu/cortexm: move CPU_ARCH/FAM to Makefile.features
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@ -1,3 +1,5 @@
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CPU_ARCH = cortex-m3
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FEATURES_PROVIDED += periph_cpuid
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FEATURES_PROVIDED += periph_gpio periph_gpio_irq
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FEATURES_PROVIDED += periph_hwrng
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CPU_ARCH = cortex-m3
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include $(RIOTMAKE)/arch/cortexm.inc.mk
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CPU_ARCH = cortex-m3
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-include $(RIOTCPU)/cc26xx_cc13xx/Makefile.features
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CPU_ARCH = cortex-m3
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CPU_VARIANT = x0
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VECTORS_O = $(BINDIR)/cc26xx_cc13xx/vectors.o
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CPU_ARCH = cortex-m4f
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-include $(RIOTCPU)/cc26xx_cc13xx/Makefile.features
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CPU_ARCH = cortex-m4f
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CPU_VARIANT = x2
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VECTORS_O = $(BINDIR)/cc26xx_cc13xx/vectors.o
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CPU_ARCH = cortex-m4f
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FEATURES_PROVIDED += periph_cpuid
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FEATURES_PROVIDED += periph_gpio periph_gpio_irq
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CPU_ARCH = cortex-m4f
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include $(RIOTMAKE)/arch/cortexm.inc.mk
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CPU_ARCH = cortex-m4f
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-include $(RIOTCPU)/cortexm_common/Makefile.features
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CPU_ARCH = cortex-m4f
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include $(RIOTMAKE)/arch/cortexm.inc.mk
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include $(RIOTCPU)/stellaris_common/Makefile.include
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CPU_ARCH = cortex-m3
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# This CPU only implements one CPU_MODEL with the same name
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CPU_MODEL = lpc1768
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FEATURES_PROVIDED += periph_cpuid
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FEATURES_PROVIDED += periph_pm
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CPU_ARCH = cortex-m3
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include $(RIOTMAKE)/arch/cortexm.inc.mk
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@ -1 +1,4 @@
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CPU_ARCH = cortex-m0
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CPU_FAM = nrf51
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-include $(RIOTCPU)/nrf5x_common/Makefile.features
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CPU_ARCH = cortex-m0
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CPU_FAM = nrf51
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include $(RIOTCPU)/nrf5x_common/Makefile.include
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include $(RIOTMAKE)/arch/cortexm.inc.mk
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CPU_ARCH = cortex-m4f
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CPU_FAM = nrf52
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# The ADC does not depend on any board configuration, so always available
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FEATURES_PROVIDED += periph_adc
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CPU_ARCH = cortex-m4f
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CPU_FAM = nrf52
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# Slot size is determined by "((total_flash_size - RIOTBOOT_LEN) / 2)".
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# If RIOTBOOT_LEN uses an uneven number of flashpages, the remainder of the
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# flash cannot be divided by two slots while staying FLASHPAGE_SIZE aligned.
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CPU_ARCH = cortex-m3
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CPU_FAM = sam3
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FEATURES_PROVIDED += periph_cpuid
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FEATURES_PROVIDED += periph_hwrng
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CPU_ARCH = cortex-m3
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CPU_FAM = sam3
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include $(RIOTCPU)/sam_common/Makefile.include
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include $(RIOTMAKE)/arch/cortexm.inc.mk
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CPU_ARCH = cortex-m0plus
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CPU_FAM = samd21
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FEATURES_PROVIDED += puf_sram
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-include $(RIOTCPU)/sam0_common/Makefile.features
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CPU_ARCH = cortex-m0plus
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CPU_FAM = samd21
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ifneq (,$(filter samd21%a,$(CPU_MODEL)))
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CFLAGS += -DCPU_SAMD21A
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endif
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CPU_ARCH = cortex-m4f
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CPU_FAM = samd5x
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FEATURES_PROVIDED += periph_hwrng
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FEATURES_PROVIDED += backup_ram
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CPU_ARCH = cortex-m4f
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CPU_FAM = samd5x
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ifneq (,$(filter samd51%,$(CPU_MODEL)))
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CFLAGS += -DCPU_SAMD51
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endif
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CPU_ARCH = cortex-m23
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CPU_FAM = saml1x
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FEATURES_PROVIDED += periph_hwrng
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include $(RIOTCPU)/sam0_common/Makefile.features
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CPU_ARCH = cortex-m23
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ifneq (,$(filter saml10%,$(CPU_MODEL)))
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CFLAGS += -DCPU_SAML10
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endif
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CPU_ARCH = cortex-m0plus
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CPU_FAM = saml21
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# The SAMR30 line of MCUs does not contain a TRNG
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BOARDS_WITHOUT_HWRNG += samr30-xpro
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CPU_ARCH = cortex-m0plus
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CPU_FAM = saml21
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ifneq (,$(filter saml21%a,$(CPU_MODEL)))
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CFLAGS += -DCPU_SAML21A
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endif
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CPU_ARCH = cortex-m0
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CPU_FAM = stm32f0
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ifeq (,$(filter nucleo-f031k6,$(BOARD)))
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FEATURES_PROVIDED += periph_flashpage
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FEATURES_PROVIDED += periph_flashpage_raw
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@ -1,5 +1,2 @@
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CPU_ARCH = cortex-m0
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CPU_FAM = stm32f0
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include $(RIOTCPU)/stm32_common/Makefile.include
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include $(RIOTMAKE)/arch/cortexm.inc.mk
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CPU_ARCH = cortex-m3
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CPU_FAM = stm32f1
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FEATURES_PROVIDED += periph_flashpage
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FEATURES_PROVIDED += periph_flashpage_raw
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FEATURES_PROVIDED += periph_rtc
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CPU_ARCH = cortex-m3
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CPU_FAM = stm32f1
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include $(RIOTCPU)/stm32_common/Makefile.include
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include $(RIOTMAKE)/arch/cortexm.inc.mk
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CPU_ARCH = cortex-m3
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CPU_FAM = stm32f2
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FEATURES_PROVIDED += periph_hwrng
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-include $(RIOTCPU)/stm32_common/Makefile.features
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CPU_ARCH = cortex-m3
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CPU_FAM = stm32f2
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# STM32F2 uses sectors instead of pages, where the minimum sector length is 16KB
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# (the first sector), therefore RIOTBOOT_LEN must be 16KB to cover a whole sector.
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RIOTBOOT_LEN ?= 0x4000
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CPU_ARCH = cortex-m4f
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CPU_FAM = stm32f3
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FEATURES_PROVIDED += periph_flashpage
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FEATURES_PROVIDED += periph_flashpage_raw
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CPU_ARCH = cortex-m4f
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CPU_FAM = stm32f3
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include $(RIOTCPU)/stm32_common/Makefile.include
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include $(RIOTMAKE)/arch/cortexm.inc.mk
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CPU_ARCH = cortex-m4f
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CPU_FAM = stm32f4
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FEATURES_PROVIDED += periph_hwrng
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# the granularity of provided feature definition for STMs is currently by CPU
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CPU_ARCH = cortex-m4f
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CPU_FAM = stm32f4
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# STM32F4 uses sectors instead of pages, where the minimum sector length is 16KB
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# (the first sector), therefore RIOTBOOT_LEN must be 16KB to cover a whole sector.
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RIOTBOOT_LEN ?= 0x4000
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CPU_ARCH = cortex-m7
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CPU_FAM = stm32f7
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FEATURES_PROVIDED += periph_hwrng
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-include $(RIOTCPU)/stm32_common/Makefile.features
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CPU_ARCH = cortex-m7
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CPU_FAM = stm32f7
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# STM32F7 uses sectors instead of pages, where the minimum sector length is 16KB or
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# 32kB (the first sector), depending on the CPU_MODEL. Therefore RIOTBOOT_LEN must
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# be 16KB or 32kB to cover a whole sector.
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CPU_ARCH = cortex-m0plus
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CPU_FAM = stm32l0
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FEATURES_PROVIDED += periph_eeprom
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FEATURES_PROVIDED += periph_flashpage
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FEATURES_PROVIDED += periph_flashpage_raw
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CPU_ARCH = cortex-m0plus
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CPU_FAM = stm32l0
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include $(RIOTCPU)/stm32_common/Makefile.include
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include $(RIOTMAKE)/arch/cortexm.inc.mk
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CPU_ARCH = cortex-m3
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CPU_FAM = stm32l1
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FEATURES_PROVIDED += periph_eeprom
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FEATURES_PROVIDED += periph_flashpage
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FEATURES_PROVIDED += periph_flashpage_raw
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CPU_ARCH = cortex-m3
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CPU_FAM = stm32l1
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include $(RIOTCPU)/stm32_common/Makefile.include
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include $(RIOTMAKE)/arch/cortexm.inc.mk
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CPU_ARCH = cortex-m4f
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CPU_FAM = stm32l4
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FEATURES_PROVIDED += periph_flashpage
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FEATURES_PROVIDED += periph_flashpage_raw
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FEATURES_PROVIDED += periph_hwrng
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CPU_ARCH = cortex-m4f
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CPU_FAM = stm32l4
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# "The Vector table must be naturally aligned to a power of two whose alignment
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# value is greater than or equal to number of Exceptions supported x 4"
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# CPU_IRQ_NUMOFF for stm32l4 boards is < 91+16 so (107*4 bytes = 428 bytes ~= 0x200)
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