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boards/stm32f723e-disco: add FMC support
f
This commit is contained in:
Gunar Schorcht
parent
aaaf961de3
commit
d75736b8ba
@ -14,6 +14,9 @@ config BOARD_STM32F723E_DISCO
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select CPU_MODEL_STM32F723IE
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# Put defined MCU peripherals here (in alphabetical order)
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select HAS_PERIPH_FMC
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select HAS_PERIPH_FMC_16BIT
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select HAS_PERIPH_FMC_NOR_SRAM
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select HAS_PERIPH_I2C
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select HAS_PERIPH_RTC
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select HAS_PERIPH_RTT
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@ -10,6 +10,10 @@ ifneq (,$(filter touch_dev,$(USEMODULE)))
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USEMODULE += ft5x06
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endif
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ifneq (,$(filter periph_fmc,$(USEMODULE)))
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FEATURES_REQUIRED += periph_fmc_16bit
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endif
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ifneq (,$(filter periph_spi,$(USEMODULE)))
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# The LED pin is also used for SPI
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DISABLE_MODULE += periph_init_led0
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@ -3,6 +3,9 @@ CPU = stm32
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CPU_MODEL = stm32f723ie
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# Put defined MCU peripherals here (in alphabetical order)
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FEATURES_PROVIDED += periph_fmc
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FEATURES_PROVIDED += periph_fmc_16bit
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FEATURES_PROVIDED += periph_fmc_nor_sram
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FEATURES_PROVIDED += periph_i2c
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FEATURES_PROVIDED += periph_rtc
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FEATURES_PROVIDED += periph_rtt
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@ -13,3 +13,8 @@ PROGRAMMERS_SUPPORTED += openocd
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# The board can become un-flashable after some execution or after being plugged,
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# use connect_assert_srst to always be able to flash or reset the board.
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OPENOCD_RESET_USE_CONNECT_ASSERT_SRST ?= 1
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# Since only 18 of the 19 address lines are connected, only 512 kByte of the
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# 1 MByte PSRAM can be used.
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FMC_RAM_ADDR=0x60000000
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FMC_RAM_LEN=512K
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@ -232,6 +232,107 @@ static const spi_conf_t spi_config[] = {
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#define SPI_NUMOF ARRAY_SIZE(spi_config)
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/** @} */
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/**
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* @name FMC configuration
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* @{
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*/
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/**
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* @brief FMC controller configuration
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*/
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static const fmc_conf_t fmc_config = {
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.bus = AHB3,
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.rcc_mask = RCC_AHB3ENR_FMCEN,
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#if MODULE_PERIPH_FMC_NOR_SRAM
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.ne1_pin = { .pin = GPIO_PIN(PORT_D, 7), .af = GPIO_AF12, }, /* PSRAM_NE1 signal, subbank 1 */
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.ne2_pin = { .pin = GPIO_PIN(PORT_G, 9), .af = GPIO_AF12, }, /* LCD_NE signal, subbank 2 */
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.noe_pin = { .pin = GPIO_PIN(PORT_D, 4), .af = GPIO_AF12, }, /* LCD_PSRAM_NOE */
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.nwe_pin = { .pin = GPIO_PIN(PORT_D, 5), .af = GPIO_AF12, }, /* LCD_PSRAM_NWE signal */
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.addr = {
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{ .pin = GPIO_PIN(PORT_F, 0), .af = GPIO_AF12, }, /* PSRAM_A0 / LCD_RS signal */
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{ .pin = GPIO_PIN(PORT_F, 1), .af = GPIO_AF12, }, /* PSRAM_A1 signal */
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{ .pin = GPIO_PIN(PORT_F, 2), .af = GPIO_AF12, }, /* PSRAM_A2 signal */
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{ .pin = GPIO_PIN(PORT_F, 3), .af = GPIO_AF12, }, /* PSRAM_A3 signal */
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{ .pin = GPIO_PIN(PORT_F, 4), .af = GPIO_AF12, }, /* PSRAM_A4 signal */
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{ .pin = GPIO_PIN(PORT_F, 5), .af = GPIO_AF12, }, /* PSRAM_A5 signal */
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{ .pin = GPIO_PIN(PORT_F, 12), .af = GPIO_AF12, }, /* PSRAM_A6 signal */
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{ .pin = GPIO_PIN(PORT_F, 13), .af = GPIO_AF12, }, /* PSRAM_A7 signal */
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{ .pin = GPIO_PIN(PORT_F, 14), .af = GPIO_AF12, }, /* PSRAM_A8 signal */
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{ .pin = GPIO_PIN(PORT_F, 15), .af = GPIO_AF12, }, /* PSRAM_A9 signal */
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{ .pin = GPIO_PIN(PORT_G, 0), .af = GPIO_AF12, }, /* PSRAM_A10 signal */
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{ .pin = GPIO_PIN(PORT_G, 1), .af = GPIO_AF12, }, /* PSRAM_A11 signal */
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{ .pin = GPIO_PIN(PORT_G, 2), .af = GPIO_AF12, }, /* PSRAM_A12 signal */
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{ .pin = GPIO_PIN(PORT_G, 3), .af = GPIO_AF12, }, /* PSRAM_A13 signal */
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{ .pin = GPIO_PIN(PORT_G, 4), .af = GPIO_AF12, }, /* PSRAM_A14 signal */
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{ .pin = GPIO_PIN(PORT_G, 5), .af = GPIO_AF12, }, /* PSRAM_A15 signal */
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{ .pin = GPIO_PIN(PORT_D, 11), .af = GPIO_AF12, }, /* PSRAM_A16 signal */
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{ .pin = GPIO_PIN(PORT_D, 12), .af = GPIO_AF12, }, /* PSRAM_A17 signal */
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},
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#endif
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.data = {
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{ .pin = GPIO_PIN(PORT_D, 14), .af = GPIO_AF12, }, /* LCD_PSRAM_D0 signal */
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{ .pin = GPIO_PIN(PORT_D, 15), .af = GPIO_AF12, }, /* LCD_PSRAM_D1 signal */
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{ .pin = GPIO_PIN(PORT_D, 0), .af = GPIO_AF12, }, /* LCD_PSRAM_D2 signal */
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{ .pin = GPIO_PIN(PORT_D, 1), .af = GPIO_AF12, }, /* LCD_PSRAM_D3 signal */
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{ .pin = GPIO_PIN(PORT_E, 7), .af = GPIO_AF12, }, /* LCD_PSRAM_D4 signal */
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{ .pin = GPIO_PIN(PORT_E, 8), .af = GPIO_AF12, }, /* LCD_PSRAM_D5 signal */
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{ .pin = GPIO_PIN(PORT_E, 9), .af = GPIO_AF12, }, /* LCD_PSRAM_D6 signal */
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{ .pin = GPIO_PIN(PORT_E, 10), .af = GPIO_AF12, }, /* LCD_PSRAM_D7 signal */
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#if MODULE_PERIPH_FMC_16BIT
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{ .pin = GPIO_PIN(PORT_E, 11), .af = GPIO_AF12, }, /* LCD_PSRAM_D8 signal */
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{ .pin = GPIO_PIN(PORT_E, 12), .af = GPIO_AF12, }, /* LCD_PSRAM_D9 signal */
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{ .pin = GPIO_PIN(PORT_E, 13), .af = GPIO_AF12, }, /* LCD_PSRAM_D10 signal */
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{ .pin = GPIO_PIN(PORT_E, 14), .af = GPIO_AF12, }, /* LCD_PSRAM_D11 signal */
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{ .pin = GPIO_PIN(PORT_E, 15), .af = GPIO_AF12, }, /* LCD_PSRAM_D12 signal */
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{ .pin = GPIO_PIN(PORT_D, 8), .af = GPIO_AF12, }, /* LCD_PSRAM_D13 signal */
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{ .pin = GPIO_PIN(PORT_D, 9), .af = GPIO_AF12, }, /* LCD_PSRAM_D14 signal */
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{ .pin = GPIO_PIN(PORT_D, 10), .af = GPIO_AF12, }, /* LCD_PSRAM_D15 signal */
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#endif
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},
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.nbl0_pin = { .pin = GPIO_PIN(PORT_E, 0), .af = GPIO_AF12, }, /* PSRAM_NBL0 signal (LB) */
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.nbl1_pin = { .pin = GPIO_PIN(PORT_E, 1), .af = GPIO_AF12, }, /* PSRAM_NBL1 signal (UB) */
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};
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/**
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* @brief FMC Bank configuration
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*
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* The board has a PSRAM IS66WV51216EBLL-55BLI with MBit on-board.
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* It is organized in 512K x 16 bits and connected to bank 1, subbank 1
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* at address 0x60000000.
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*
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* @note A18 of the PSRAM is not used. Therefore, only 256K x 16 bits
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* (512 kByte) of the 1 MByte PSRAM can be used.
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*
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* The LCD display of the board is connected to bank 1, subbank2
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* at address 0x64000000.
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*/
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static const fmc_bank_conf_t fmc_bank_config[] = {
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/* bank 1, subbank 1 is used for PSRAM with asynchronuous
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* access in Mode 1, i.e. write timings are not used */
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{
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.bank = FMC_BANK_1,
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.mem_type = FMC_SRAM,
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.data_width = FMC_BUS_WIDTH_16BIT,
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.address = 0x60000000, /* Bank 1, subbank 1 is mapped to 0x60000000 */
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.size = KiB(512), /* Size in byte, 256K x 16 bit */
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.nor_sram = {
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.sub_bank = 1,
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.ext_mode = false, /* Mode 1 used, no separate w_timing */
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/* timings for IS66WV51216EBLL-55BLI
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@216 MHz AHB clock */
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.r_timing = { .addr_setup = 13, /* t_AA = max 60 ns (13 HCLKs a 4.63 ns) */
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.data_setup = 6, /* t_SD = min 25 ns (6 HCLKs a 4.63 ns) */
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.bus_turnaround = 3, }, /* 3 HCLKs a 4.63 ns */
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},
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},
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};
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/**
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* @brief Number of configured FMC banks
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*/
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#define FMC_BANK_NUMOF ARRAY_SIZE(fmc_bank_config)
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/** @} */
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#ifdef __cplusplus
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}
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#endif
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