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cpu/stm32: Fix CLOCK_CORECLOCK on stm32l0/l1

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With the previous order of the operation there was a loss of precision
when using certain values as the divider
This commit is contained in:
Jean-Pierre De Jesus DIAZ 2022-03-01 17:08:02 +01:00
parent a17ff53ecf
commit d64bbdffe5
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1 changed files with 1 additions and 1 deletions
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cpu/stm32/include/clk/l0l1/cfg_clock_default.h
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@ -71,7 +71,7 @@ extern "C" {
* PLL_MUL: multiplier, allowed values: 3, 4, 6, 8, 12, 16, 24, 32, 48. Default is 4.
* CORECLOCK -> 32MHz MAX!
*/
#define CLOCK_CORECLOCK ((CLOCK_PLL_SRC / CONFIG_CLOCK_PLL_DIV) * CONFIG_CLOCK_PLL_MUL)
#define CLOCK_CORECLOCK ((CLOCK_PLL_SRC * CONFIG_CLOCK_PLL_MUL) / CONFIG_CLOCK_PLL_DIV)
#if CLOCK_CORECLOCK > MHZ(32)
#error "SYSCLK cannot exceed 32MHz"
#endif