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Merge pull request #1357 from haukepetersen/fix_cortexm3_threading
cpu: cortex-m3_common: cleanup thread_arch.c
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commit
d56e90a3f0
@ -20,14 +20,15 @@
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*/
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#include <stdint.h>
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#include <stdio.h>
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#include "arch/thread_arch.h"
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#include "thread.h"
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#include "sched.h"
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#include "irq.h"
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#include "cpu.h"
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#include "kernel_internal.h"
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/**
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* @name noticeable marker marking the beginning of a stack segment
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*
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@ -41,10 +42,8 @@
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*/
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#define EXCEPT_RET_TASK_MODE (0xfffffffd)
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static void context_save(void);
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static void context_restore(void) NORETURN;
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static void enter_thread_mode(void) NORETURN;
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/**
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* Cortex-M3 knows stacks and handles register backups, so use different stack frame layout
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@ -92,103 +91,89 @@ char *thread_arch_stack_init(void (*task_func)(void), void *stack_start, int st
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*stk = i;
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}
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/* lr means exception return code */
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/* put LR to trigger return to thread stack pointer */
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stk--;
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*stk = (uint32_t)EXCEPT_RET_TASK_MODE; /* return to task-mode main stack pointer */
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*stk = (uint32_t)EXCEPT_RET_TASK_MODE;
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return (char*) stk;
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}
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void thread_arch_stack_print(void)
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{
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/* TODO */
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int count = 0;
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uint32_t *sp = (uint32_t *)sched_active_thread->sp;
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printf("printing the current stack of thread %u\n", thread_getpid());
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printf(" address: data:\n");
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do {
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printf(" 0x%08x: 0x%08x\n", (unsigned int)sp, (unsigned int)*sp);
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sp++;
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count++;
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} while (*sp != STACK_MARKER);
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printf("current stack size: %u byte\n", count);
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}
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void thread_arch_start_threading(void)
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__attribute__((naked)) void thread_arch_start_threading(void)
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{
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sched_run();
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/* enable IRQs to make sure the SVC interrupt is reachable */
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enableIRQ();
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enter_thread_mode();
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}
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/**
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* @brief Set the MCU into Thread-Mode and load the initial task from the stack and run it
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*/
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void NORETURN enter_thread_mode(void)
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{
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/* switch to user mode use PSP instead of MSP in ISR Mode*/
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CONTROL_Type mode;
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mode.w = __get_CONTROL();
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mode.b.SPSEL = 1; /* select PSP */
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mode.b.nPRIV = 0; /* privilege */
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__set_CONTROL(mode.w);
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/* load pdc->stackpointer in r0 */
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asm("ldr r0, =sched_active_thread" ); /* r0 = &sched_active_thread */
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asm("ldr r0, [r0]" ); /* r0 = *r0 = sched_active_thread */
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asm("ldr sp, [r0]" ); /* sp = r0 restore stack pointer*/
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asm("pop {r4}" ); /* skip exception return */
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asm("pop {r4-r11}" );
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asm("pop {r0-r3,r12,lr}" ); /* get registers from stack */
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asm("pop {r4}" ); /* get PC */
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asm("pop {r5}" ); /* discard the xPSR entry */
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asm("mov pc, r4" ); /* load PC */
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UNREACHABLE();
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/* trigger the SVC interrupt which will get and execute the next thread */
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asm("svc 0x01");
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}
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void thread_arch_yield(void)
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{
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if (irq_arch_in()) {
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SCB->ICSR |= SCB_ICSR_PENDSVSET_Msk; /* set PendSV Bit */
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}
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else {
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asm("svc 0x01\n"); /* trigger SVC interrupt, which will trigger the pendSV (needed?) */
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}
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}
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/**
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* @brief SVC interrupt handler (to be discussed if this is really needed)
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*/
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__attribute__((naked)) void isr_svc(void)
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{
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SCB->ICSR |= SCB_ICSR_PENDSVSET_Msk; /* trigger the pendsv interrupt */
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asm("bx LR" ); /* load exception return value to PC causes end of exception*/
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}
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__attribute__((naked)) void isr_pendsv(void)
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{
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context_save();
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sched_run();
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context_restore();
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/* trigger the PENDSV interrupt to run scheduler and schedule new thread if applicable */
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SCB->ICSR |= SCB_ICSR_PENDSVSET_Msk;
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}
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__attribute__((always_inline)) static __INLINE void context_save(void)
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{
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/* {r0-r3,r12,LR,PC,xPSR} are saved automatically on exception entry */
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/* save unsaved registers */
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asm("mrs r0, psp" ); /* get stack pointer from user mode */
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asm("stmdb r0!,{r4-r11}" ); /* save regs */
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asm("stmdb r0!,{lr}" ); /* exception return value */
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/* asm("vstmdb sp!, {s16-s31}" ); */ /* TODO save FPU registers if needed */
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asm("ldr r1, =sched_active_thread" ); /* load address of current tcb */
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asm("ldr r1, [r1]" ); /* dereference pdc */
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asm("str r0, [r1]" ); /* write r0 to pdc->sp means current threads stack pointer */
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/* save unsaved registers onto the stack */
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asm("mrs r0, psp" ); /* get stack pointer from user mode */
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asm("stmdb r0!,{r4-r11}" ); /* save regs */
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asm("stmdb r0!,{lr}" ); /* exception return value */
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asm("ldr r1, =sched_active_thread" ); /* load address of current TCB */
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asm("ldr r1, [r1]" ); /* dereference TCB */
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asm("str r0, [r1]" ); /* write r0 to tcb->sp */
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}
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__attribute__((always_inline)) static __INLINE void context_restore(void)
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{
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asm("ldr r0, =sched_active_thread" ); /* load address of current TCB */
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asm("ldr r0, [r0]" ); /* dereference TCB */
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asm("ldr r1, [r0]" ); /* load tcb->sp to register 1 */
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asm("ldmia r1!, {r0}" ); /* restore exception return value from stack */
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/* asm("pop {s16-s31}" ); */ /* TODO load FPU register if needed depends on r0 exret */
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asm("ldmia r1!, {r4-r11}" ); /* restore other registers */
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asm("msr psp, r1" ); /* restore PSP register (user mode SP)*/
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asm("bx r0" ); /* load exception return value to PC causes end of exception*/
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/* restore registers from stack */
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asm("ldr r0, =sched_active_thread" ); /* load address of current TCB */
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asm("ldr r0, [r0]" ); /* dereference TCB */
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asm("ldr r1, [r0]" ); /* load tcb->sp to register 1 */
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asm("ldmia r1!, {r0}" ); /* restore exception return value from stack */
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asm("ldmia r1!, {r4-r11}" ); /* restore other registers */
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asm("msr psp, r1" ); /* restore PSP register (user mode SP) */
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asm("bx r0" ); /* load exception return value to PC */
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/* {r0-r3,r12,LR,PC,xPSR} are restored automatically on exception return */
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UNREACHABLE();
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}
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/**
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* @brief The svc is used for running the scheduler and scheduling a new task during start-up or
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* after a thread has exited
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*/
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__attribute__((naked)) void isr_svc(void)
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{
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sched_run();
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context_restore();
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}
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/**
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* @brief All task switching activity is carried out int the pendSV interrupt
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*/
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__attribute__((naked)) void isr_pendsv(void)
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{
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context_save();
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sched_run();
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context_restore();
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}
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