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boards/sodaq-sara-aff: Initial support
This commit is contained in:
Leandro Lanzieri
parent
77c9cc4041
commit
d53fbb0045
3
boards/sodaq-sara-aff/Makefile
Normal file
3
boards/sodaq-sara-aff/Makefile
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@ -0,0 +1,3 @@
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MODULE = board
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include $(RIOTBASE)/Makefile.base
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3
boards/sodaq-sara-aff/Makefile.dep
Normal file
3
boards/sodaq-sara-aff/Makefile.dep
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@ -0,0 +1,3 @@
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ifneq (,$(filter saul_default,$(USEMODULE)))
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USEMODULE += saul_gpio
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endif
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11
boards/sodaq-sara-aff/Makefile.features
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11
boards/sodaq-sara-aff/Makefile.features
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@ -0,0 +1,11 @@
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# Put defined MCU peripherals here (in alphabetical order)
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FEATURES_PROVIDED += periph_adc
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FEATURES_PROVIDED += periph_gpio periph_gpio_irq
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FEATURES_PROVIDED += periph_i2c
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FEATURES_PROVIDED += periph_rtc
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FEATURES_PROVIDED += periph_rtt
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FEATURES_PROVIDED += periph_spi
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FEATURES_PROVIDED += periph_timer
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FEATURES_PROVIDED += periph_uart
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include $(RIOTCPU)/samd21/Makefile.features
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19
boards/sodaq-sara-aff/Makefile.include
Normal file
19
boards/sodaq-sara-aff/Makefile.include
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@ -0,0 +1,19 @@
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# define the cpu used by the SODAQ SARA AFF boards
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export CPU = samd21
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export CPU_MODEL = samd21j18a
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#export needed for flash rule
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export PORT_LINUX ?= /dev/ttyACM0
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export PORT_DARWIN ?= $(firstword $(sort $(wildcard /dev/tty.usbmodem*)))
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# setup serial terminal
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include $(RIOTMAKE)/tools/serial.inc.mk
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# setup the flash tool used
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# we use BOSSA to flash this board since there's an Arduino bootloader
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# preflashed on it. ROM_OFFSET skips the space taken by such bootloader.
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ROM_OFFSET ?= 0x2000
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include $(RIOTMAKE)/tools/bossa.inc.mk
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# setup the boards dependencies
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include $(RIOTBOARD)/$(BOARD)/Makefile.dep
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54
boards/sodaq-sara-aff/board.c
Normal file
54
boards/sodaq-sara-aff/board.c
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@ -0,0 +1,54 @@
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/*
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* Copyright (C) 2018 HAW Hamburg
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup boards_sodaq-sara-aff
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* @{
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*
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* @file
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* @brief Board common implementations for the SODAQ SARA AFF boards
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*
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* @author Leandro Lanzieri <leandro.lanzieri@haw-hamburg.de>
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* @}
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*/
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#include "cpu.h"
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#include "board.h"
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#include "periph/gpio.h"
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void board_init(void)
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{
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#ifdef AUTO_INIT_LED0
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/* The LED pin is also used for SPI, so we enable it
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only if explicitly wanted by the user */
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LED0_OFF;
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gpio_init(LED0_PIN, GPIO_OUT);
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#endif
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LED_RED_OFF;
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gpio_init(LED_RED_PIN, GPIO_OUT);
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LED_GREEN_OFF;
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gpio_init(LED_GREEN_PIN, GPIO_OUT);
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LED_BLUE_OFF;
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gpio_init(LED_BLUE_PIN, GPIO_OUT);
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/* set NB-IoT device off by default */
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NB_IOT_DISABLE;
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gpio_init(NB_IOT_ENABLE_PIN, GPIO_OUT);
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NB_IOT_TX_EN_OFF;
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gpio_init(NB_IOT_TX_EN_PIN, GPIO_OUT);
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NB_IOT_TOGGLE_ON;
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gpio_init(NB_IOT_TOGGLE_PIN, GPIO_OUT);
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/* set GPS off by default */
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GPS_ENABLE_OFF;
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gpio_init(GPS_ENABLE_PIN, GPIO_OUT);
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/* initialize the CPU */
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cpu_init();
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}
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32
boards/sodaq-sara-aff/doc.txt
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32
boards/sodaq-sara-aff/doc.txt
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/**
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* @defgroup boards_sodaq-sara-aff SODAQ SARA AFF
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* @ingroup boards
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* @brief Support for the SODAQ SARA AFF boards
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*
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* ### General information
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*
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* General information about this board can be found on the
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* [SODAQ support](http://support.sodaq.com/sodaq-one/sodaq-sara-r410m/)
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* website.
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* 
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*
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* ### Flash the board
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*
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* 1. Put the board in bootloader mode by double tapping the reset button.<br/>
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* When the board is in bootloader mode, the user led (blue) oscillates
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* smoothly.
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*
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*
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* 2. Use `BOARD=sodaq-sara-aff` with the `make` command.<br/>
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* Example with `hello-world` application:
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* ```
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* make BOARD=sodaq-sara-aff -C examples/hello-world flash
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* ```
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*
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* ### Accessing STDIO via UART
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*
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* To access the STDIO of RIOT, a FTDI to USB converter needs to be plugged to
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* the RX/TX pins on the board.
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*
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*/
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168
boards/sodaq-sara-aff/include/board.h
Normal file
168
boards/sodaq-sara-aff/include/board.h
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@ -0,0 +1,168 @@
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/*
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* Copyright (C) 2018 HAW Hamburg
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup boards_sodaq-sara-aff
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* @{
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*
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* @file
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* @brief Board specific definitions for the SODAQ SARA AFF boards
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*
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* @author Leandro Lanzieri <leandro.lanzieri@haw-hamburg.de>
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*/
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#ifndef BOARD_H
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#define BOARD_H
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#include "cpu.h"
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#include "periph_conf.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @name xtimer configuration
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* @{
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*/
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#define XTIMER_WIDTH (16)
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/** @} */
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/**
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* @name LED pin definitions and handlers
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* @{
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*/
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#define LED0_PIN GPIO_PIN(PA, 21)
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#define LED0_PORT PORT->Group[PA]
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#define LED0_MASK (1 << 21)
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#define LED0_OFF (LED0_PORT.OUTCLR.reg = LED0_MASK)
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#define LED0_ON (LED0_PORT.OUTSET.reg = LED0_MASK)
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#define LED0_TOGGLE (LED0_PORT.OUTTGL.reg = LED0_MASK)
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#define LED1_PIN GPIO_PIN(PA, 12)
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#define LED1_PORT PORT->Group[PA]
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#define LED1_MASK (1 << 12)
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#define LED1_OFF (LED1_PORT.OUTSET.reg = LED1_MASK)
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#define LED1_ON (LED1_PORT.OUTCLR.reg = LED1_MASK)
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#define LED1_TOGGLE (LED1_PORT.OUTTGL.reg = LED1_MASK)
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#define LED_RED_PIN LED1_PIN
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#define LED_RED_OFF LED1_OFF
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#define LED_RED_ON LED1_ON
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#define LED_RED_TOGGLE LED1_TOGGLE
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#define LED2_PIN GPIO_PIN(PB, 15)
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#define LED2_PORT PORT->Group[PB]
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#define LED2_MASK (1 << 15)
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#define LED2_OFF (LED2_PORT.OUTSET.reg = LED2_MASK)
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#define LED2_ON (LED2_PORT.OUTCLR.reg = LED2_MASK)
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#define LED2_TOGGLE (LED2_PORT.OUTTGL.reg = LED2_MASK)
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#define LED_GREEN_PIN LED2_PIN
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#define LED_GREEN_OFF LED2_OFF
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#define LED_GREEN_ON LED2_ON
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#define LED_GREEN_TOGGLE LED2_TOGGLE
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#define LED3_PIN GPIO_PIN(PA, 13)
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#define LED3_PORT PORT->Group[PA]
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#define LED3_MASK (1 << 13)
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#define LED3_OFF (LED3_PORT.OUTSET.reg = LED3_MASK)
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#define LED3_ON (LED3_PORT.OUTCLR.reg = LED3_MASK)
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#define LED3_TOGGLE (LED3_PORT.OUTTGL.reg = LED3_MASK)
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#define LED_BLUE_PIN LED3_PIN
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#define LED_BLUE_OFF LED3_OFF
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#define LED_BLUE_ON LED3_ON
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#define LED_BLUE_TOGGLE LED3_TOGGLE
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/** @} */
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/**
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* @name GPS Time Pulse
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* @{
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*/
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#define GPS_TIMEPULSE_PIN GPIO_PIN(PA, 7)
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#define GPS_TIMEPULSE_MODE GPIO_IN
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/** @} */
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/**
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* @name GPS Enable
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* @{
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*/
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#define GPS_ENABLE_PIN GPIO_PIN(PA, 28)
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#define GPS_ENABLE_PORT PORT->Group[PA]
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#define GPS_ENABLE_MASK (1 << 28)
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#define GPS_ENABLE_ON (GPS_ENABLE_PORT.OUTSET.reg = GPS_ENABLE_MASK)
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#define GPS_ENABLE_OFF (GPS_ENABLE_PORT.OUTCLR.reg = GPS_ENABLE_MASK)
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/** @} */
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/**
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* @name NB-IoT SARA module
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* @{
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*/
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#define NB_IOT_ENABLE_PIN GPIO_PIN(PA, 27)
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#define NB_IOT_ENABLE_PORT PORT->Group[PA]
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#define NB_IOT_ENABLE_MASK (1 << 27)
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#define NB_IOT_ENABLE (NB_IOT_ENABLE_PORT.OUTSET.reg = NB_IOT_ENABLE_MASK)
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#define NB_IOT_DISABLE (NB_IOT_ENABLE_PORT.OUTCLR.reg = NB_IOT_ENABLE_MASK)
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#define NB_IOT_RESET_PIN GPIO_PIN(PB, 14)
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#define NB_IOT_RESET_PORT PORT->Group[PB]
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#define NB_IOT_RESET_MASK (1 << 14)
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#define NB_IOT_RESET_ON (NB_IOT_RESET_PORT.OUTSET.reg = NB_IOT_RESET_MASK)
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#define NB_IOT_RESET_OFF (NB_IOT_RESET_PORT.OUTCLR.reg = NB_IOT_RESET_MASK)
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#define NB_IOT_RESET_PIN GPIO_PIN(PB, 14)
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#define NB_IOT_RESET_PORT PORT->Group[PB]
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#define NB_IOT_RESET_MASK (1 << 14)
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#define NB_IOT_RESET_ON (NB_IOT_RESET_PORT.OUTSET.reg = NB_IOT_RESET_MASK)
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#define NB_IOT_RESET_OFF (NB_IOT_RESET_PORT.OUTCLR.reg = NB_IOT_RESET_MASK)
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#define NB_IOT_TX_EN_PIN GPIO_PIN(PB, 13)
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#define NB_IOT_TX_EN_PORT PORT->Group[PB]
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#define NB_IOT_TX_EN_MASK (1 << 13)
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#define NB_IOT_TX_EN_ON (NB_IOT_TX_EN_PORT.OUTSET.reg = NB_IOT_TX_EN_MASK)
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#define NB_IOT_TX_EN_OFF (NB_IOT_TX_EN_PORT.OUTCLR.reg = NB_IOT_TX_EN_MASK)
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#define NB_IOT_TOGGLE_PIN GPIO_PIN(PB, 17)
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#define NB_IOT_TOGGLE_PORT PORT->Group[PB]
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#define NB_IOT_TOGGLE_MASK (1 << 17)
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#define NB_IOT_TOGGLE_ON (NB_IOT_TOGGLE_PORT.OUTSET.reg = NB_IOT_TOGGLE_MASK)
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#define NB_IOT_TOGGLE_OFF (NB_IOT_TOGGLE_PORT.OUTCLR.reg = NB_IOT_TOGGLE_MASK)
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/** @} */
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/**
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* @brief Initialize board specific hardware, including clock, LEDs and std-IO
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*/
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void board_init(void);
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#ifdef __cplusplus
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}
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#endif
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#endif /* BOARD_H */
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/** @} */
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64
boards/sodaq-sara-aff/include/gpio_params.h
Normal file
64
boards/sodaq-sara-aff/include/gpio_params.h
Normal file
@ -0,0 +1,64 @@
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/*
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* Copyright (C) 2018 HAW Hamburg
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
|
||||
* directory for more details.
|
||||
*/
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/**
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* @ingroup boards_sodaq-sara-aff
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* @{
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*
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* @file
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* @brief Board specific configuration of direct mapped GPIOs
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*
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* @author Leandro Lanzieri <leandro.lanzieri@haw-hamburg.de>
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*/
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#ifndef GPIO_PARAMS_H
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#define GPIO_PARAMS_H
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#include "board.h"
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#include "saul/periph.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @brief GPIO pin configuration
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*/
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static const saul_gpio_params_t saul_gpio_params[] =
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{
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{
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.name = "LED Builtin",
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.pin = LED0_PIN,
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.mode = GPIO_OUT
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},
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{
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.name = "LED Red",
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.pin = LED1_PIN,
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.mode = GPIO_OUT,
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.flags = (SAUL_GPIO_INVERTED | SAUL_GPIO_INIT_CLEAR)
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},
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{
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.name = "LED Green",
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.pin = LED2_PIN,
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.mode = GPIO_OUT,
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.flags = (SAUL_GPIO_INVERTED | SAUL_GPIO_INIT_CLEAR)
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},
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{
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.name = "LED Blue",
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.pin = LED3_PIN,
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.mode = GPIO_OUT,
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.flags = (SAUL_GPIO_INVERTED | SAUL_GPIO_INIT_CLEAR)
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}
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};
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#ifdef __cplusplus
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}
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#endif
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#endif /* GPIO_PARAMS_H */
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/** @} */
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240
boards/sodaq-sara-aff/include/periph_conf.h
Normal file
240
boards/sodaq-sara-aff/include/periph_conf.h
Normal file
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/*
|
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* Copyright (C) 2017 Kees Bakker, SODAQ
|
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* 2018 HAW Hamburg
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU Lesser
|
||||
* General Public License v2.1. See the file LICENSE in the top level
|
||||
* directory for more details.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @ingroup boards_sodaq-sara-aff
|
||||
* @{
|
||||
*
|
||||
* @file
|
||||
* @brief Configuration of CPU peripherals for the SODAQ SARA AFF boards
|
||||
*
|
||||
* @author Kees Bakker <kees@sodaq.com>
|
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* @author Leandro Lanzieri <leandro.lanzieri@haw-hamburg.de>
|
||||
*/
|
||||
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#ifndef PERIPH_CONF_H
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#define PERIPH_CONF_H
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||||
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||||
#include <stdint.h>
|
||||
|
||||
#include "cpu.h"
|
||||
#include "periph_cpu.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @name External oscillator and clock configuration
|
||||
*
|
||||
* For selection of the used CORECLOCK, we have implemented two choices:
|
||||
*
|
||||
* - usage of the PLL fed by the internal 8MHz oscillator divided by 8
|
||||
* - usage of the internal 8MHz oscillator directly, divided by N if needed
|
||||
*
|
||||
*
|
||||
* The PLL option allows for the usage of a wider frequency range and a more
|
||||
* stable clock with less jitter. This is why we use this option as default.
|
||||
*
|
||||
* The target frequency is computed from the PLL multiplier and the PLL divisor.
|
||||
* Use the following formula to compute your values:
|
||||
*
|
||||
* CORECLOCK = ((PLL_MUL + 1) * 1MHz) / PLL_DIV
|
||||
*
|
||||
* NOTE: The PLL circuit does not run with less than 32MHz while the maximum PLL
|
||||
* frequency is 96MHz. So PLL_MULL must be between 31 and 95!
|
||||
*
|
||||
*
|
||||
* The internal Oscillator used directly can lead to a slightly better power
|
||||
* efficiency to the cost of a less stable clock. Use this option when you know
|
||||
* what you are doing! The actual core frequency is adjusted as follows:
|
||||
*
|
||||
* CORECLOCK = 8MHz / DIV
|
||||
*
|
||||
* NOTE: A core clock frequency below 1MHz is not recommended
|
||||
*
|
||||
* @{
|
||||
*/
|
||||
#define CLOCK_USE_PLL (1)
|
||||
|
||||
#if CLOCK_USE_PLL
|
||||
/* edit these values to adjust the PLL output frequency */
|
||||
#define CLOCK_PLL_MUL (47U) /* must be >= 31 & <= 95 */
|
||||
#define CLOCK_PLL_DIV (1U) /* adjust to your needs */
|
||||
/* generate the actual used core clock frequency */
|
||||
#define CLOCK_CORECLOCK (((CLOCK_PLL_MUL + 1) * 1000000U) / CLOCK_PLL_DIV)
|
||||
#else
|
||||
/* edit this value to your needs */
|
||||
#define CLOCK_DIV (1U)
|
||||
/* generate the actual core clock frequency */
|
||||
#define CLOCK_CORECLOCK (8000000 / CLOCK_DIV)
|
||||
#endif
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name Timer peripheral configuration
|
||||
* @{
|
||||
*/
|
||||
#define TIMER_NUMOF (2U)
|
||||
#define TIMER_0_EN 1
|
||||
#define TIMER_1_EN 1
|
||||
|
||||
/* Timer 0 configuration */
|
||||
#define TIMER_0_DEV TC3->COUNT16
|
||||
#define TIMER_0_CHANNELS 2
|
||||
#define TIMER_0_MAX_VALUE (0xffff)
|
||||
#define TIMER_0_ISR isr_tc3
|
||||
|
||||
/* Timer 1 configuration */
|
||||
#define TIMER_1_DEV TC4->COUNT32
|
||||
#define TIMER_1_CHANNELS 2
|
||||
#define TIMER_1_MAX_VALUE (0xffffffff)
|
||||
#define TIMER_1_ISR isr_tc4
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name UART configuration
|
||||
* @{
|
||||
* See Table 7-1 of the SAM D21 Datasheet (p. 29)
|
||||
*/
|
||||
static const uart_conf_t uart_config[] = {
|
||||
{
|
||||
.dev = &SERCOM5->USART,
|
||||
.rx_pin = GPIO_PIN(PB, 30), /* D0, RX Pin */
|
||||
.tx_pin = GPIO_PIN(PB, 31), /* D1, TX Pin */
|
||||
.mux = GPIO_MUX_D,
|
||||
.rx_pad = UART_PAD_RX_1,
|
||||
.tx_pad = UART_PAD_TX_0,
|
||||
.flags = UART_FLAG_NONE,
|
||||
.gclk_src = GCLK_CLKCTRL_GEN_GCLK0
|
||||
},
|
||||
{
|
||||
.dev = &SERCOM0->USART,
|
||||
.rx_pin = GPIO_PIN(PA,5),
|
||||
.tx_pin = GPIO_PIN(PA,6),
|
||||
.mux = GPIO_MUX_D,
|
||||
.rx_pad = UART_PAD_RX_1,
|
||||
.tx_pad = UART_PAD_TX_2,
|
||||
.flags = UART_FLAG_NONE,
|
||||
.gclk_src = GCLK_CLKCTRL_GEN_GCLK0
|
||||
},
|
||||
};
|
||||
|
||||
/* interrupt function name mapping */
|
||||
#define UART_0_ISR isr_sercom5
|
||||
#define UART_1_ISR isr_sercom0
|
||||
|
||||
#define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0]))
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name ADC configuration
|
||||
* @{
|
||||
*/
|
||||
#define ADC_0_EN 1
|
||||
#define ADC_MAX_CHANNELS 19
|
||||
/* ADC 0 device configuration */
|
||||
#define ADC_0_DEV ADC
|
||||
#define ADC_0_IRQ ADC_IRQn
|
||||
|
||||
/* ADC 0 Default values */
|
||||
#define ADC_0_CLK_SOURCE 0 /* GCLK_GENERATOR_0 */
|
||||
#define ADC_0_PRESCALER ADC_CTRLB_PRESCALER_DIV512
|
||||
|
||||
#define ADC_0_NEG_INPUT ADC_INPUTCTRL_MUXNEG_GND
|
||||
#define ADC_0_GAIN_FACTOR_DEFAULT ADC_INPUTCTRL_GAIN_1X
|
||||
#define ADC_0_REF_DEFAULT ADC_REFCTRL_REFSEL_INT1V
|
||||
|
||||
static const adc_conf_chan_t adc_channels[] = {
|
||||
/* port, pin, muxpos */
|
||||
{GPIO_PIN(PB, 0), ADC_INPUTCTRL_MUXPOS_PIN8}, /* A0 */
|
||||
{GPIO_PIN(PB, 1), ADC_INPUTCTRL_MUXPOS_PIN9}, /* A1 */
|
||||
{GPIO_PIN(PB, 2), ADC_INPUTCTRL_MUXPOS_PIN10}, /* A2 */
|
||||
{GPIO_PIN(PB, 3), ADC_INPUTCTRL_MUXPOS_PIN11}, /* A3 */
|
||||
{GPIO_PIN(PA, 8), ADC_INPUTCTRL_MUXPOS_PIN16}, /* A4 */
|
||||
{GPIO_PIN(PA, 9), ADC_INPUTCTRL_MUXPOS_PIN17}, /* A5 */
|
||||
{GPIO_PIN(PA, 10), ADC_INPUTCTRL_MUXPOS_PIN18}, /* GROVE1/A6 */
|
||||
{GPIO_PIN(PA, 11), ADC_INPUTCTRL_MUXPOS_PIN19}, /* GROVE2/A7 */
|
||||
{GPIO_PIN(PB, 5), ADC_INPUTCTRL_MUXPOS_PIN13}, /* BAT_VOLT/A8 */
|
||||
{GPIO_PIN(PA, 2), ADC_INPUTCTRL_MUXPOS_PIN0}, /* D2/DAC */
|
||||
{GPIO_PIN(PA, 3), ADC_INPUTCTRL_MUXPOS_PIN1}, /* AREF */
|
||||
};
|
||||
|
||||
#define ADC_0_CHANNELS (11)
|
||||
#define ADC_NUMOF ADC_0_CHANNELS
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name SPI configuration
|
||||
* @{
|
||||
*/
|
||||
static const spi_conf_t spi_config[] = {
|
||||
{
|
||||
.dev = &SERCOM3->SPI,
|
||||
.miso_pin = GPIO_PIN(PA, 22),
|
||||
.mosi_pin = GPIO_PIN(PA, 20),
|
||||
.clk_pin = GPIO_PIN(PA, 21),
|
||||
.miso_mux = GPIO_MUX_C,
|
||||
.mosi_mux = GPIO_MUX_D,
|
||||
.clk_mux = GPIO_MUX_D,
|
||||
.miso_pad = SPI_PAD_MISO_0,
|
||||
.mosi_pad = SPI_PAD_MOSI_2_SCK_3
|
||||
}
|
||||
};
|
||||
|
||||
#define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name I2C configuration
|
||||
* @{
|
||||
*/
|
||||
static const i2c_conf_t i2c_config[] = {
|
||||
{
|
||||
.dev = &(SERCOM1->I2CM),
|
||||
.speed = I2C_SPEED_NORMAL,
|
||||
.scl_pin = GPIO_PIN(PA, 17),
|
||||
.sda_pin = GPIO_PIN(PA, 16),
|
||||
.mux = GPIO_MUX_C,
|
||||
.gclk_src = GCLK_CLKCTRL_GEN_GCLK0,
|
||||
.flags = I2C_FLAG_NONE
|
||||
}
|
||||
};
|
||||
#define I2C_NUMOF (sizeof(i2c_config) / sizeof(i2c_config[0]))
|
||||
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name RTC configuration
|
||||
* @{
|
||||
*/
|
||||
#define RTC_NUMOF (1U)
|
||||
#define RTC_DEV RTC->MODE2
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name RTT configuration
|
||||
* @{
|
||||
*/
|
||||
#define RTT_NUMOF (1U)
|
||||
#define RTT_DEV RTC->MODE0
|
||||
#define RTT_IRQ RTC_IRQn
|
||||
#define RTT_IRQ_PRIO 10
|
||||
#define RTT_ISR isr_rtc
|
||||
#define RTT_MAX_VALUE (0xffffffff)
|
||||
#define RTT_FREQUENCY (32768U) /* in Hz. For changes see `rtt.c` */
|
||||
#define RTT_RUNSTDBY (1) /* Keep RTT running in sleep states */
|
||||
/** @} */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* PERIPH_CONF_H */
|
||||
/** @} */
|
||||
@ -23,9 +23,9 @@ BOARD_INSUFFICIENT_MEMORY := blackpill bluepill calliope-mini cc2650-launchpad \
|
||||
saml21-xpro samr21-xpro samr30-xpro \
|
||||
seeeduino_arch-pro sensebox_samd21 slstk3401a \
|
||||
sltb001a slwstk6220a sodaq-autonomo sodaq-explorer \
|
||||
sodaq-one stk3600 stm32f3discovery yunjia-nrf51822 \
|
||||
esp8266-esp-12x esp8266-olimex-mod esp8266-sparkfun-thing \
|
||||
firefly
|
||||
sodaq-one sodaq-sara-aff stk3600 stm32f3discovery \
|
||||
yunjia-nrf51822 esp8266-esp-12x esp8266-olimex-mod \
|
||||
esp8266-sparkfun-thing firefly
|
||||
|
||||
BOARD_BLACKLIST := arduino-duemilanove arduino-mega2560 arduino-uno \
|
||||
chronos hifive1 jiminy-mega256rfr2 mega-xplained mips-malta \
|
||||
|
||||
@ -69,6 +69,7 @@ BOARD_INSUFFICIENT_MEMORY := airfy-beacon \
|
||||
sodaq-autonomo \
|
||||
sodaq-explorer \
|
||||
sodaq-one \
|
||||
sodaq-sara-aff \
|
||||
spark-core \
|
||||
stk3600 \
|
||||
stm32f0discovery \
|
||||
|
||||
Loading…
Reference in New Issue
Block a user