From ef742cddb25e4d5927c9e3fc3679af384d13cf5f Mon Sep 17 00:00:00 2001 From: Alexandre Abadie Date: Fri, 25 Sep 2020 15:56:19 +0200 Subject: [PATCH 1/6] cpu/stm32: add support for stm32g431rb --- cpu/stm32/Kconfig | 5 +++++ cpu/stm32/stm32_mem_lengths.mk | 4 +++- 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/cpu/stm32/Kconfig b/cpu/stm32/Kconfig index 75b615bba3..b63854000d 100644 --- a/cpu/stm32/Kconfig +++ b/cpu/stm32/Kconfig @@ -297,6 +297,10 @@ config CPU_MODEL_STM32G071RB select CPU_FAM_G0 # STM32G4 +config CPU_MODEL_STM32G431RB + bool + select CPU_FAM_G4 + config CPU_MODEL_STM32G474RE bool select CPU_FAM_G4 @@ -535,6 +539,7 @@ config CPU_MODEL default "stm32g071rb" if CPU_MODEL_STM32G071RB # STM32G4 + default "stm32g431rb" if CPU_MODEL_STM32G431RB default "stm32g474re" if CPU_MODEL_STM32G474RE # STM32L0 diff --git a/cpu/stm32/stm32_mem_lengths.mk b/cpu/stm32/stm32_mem_lengths.mk index 6e5e0a3a86..7b4bc9626e 100644 --- a/cpu/stm32/stm32_mem_lengths.mk +++ b/cpu/stm32/stm32_mem_lengths.mk @@ -187,7 +187,9 @@ else ifeq ($(STM32_TYPE), G) endif endif ifeq ($(STM32_FAMILY), 4) - ifeq ($(STM32_MODEL), 474) + ifeq ($(STM32_MODEL), 431) + RAM_LEN = 32K + else ifeq ($(STM32_MODEL), 474) RAM_LEN = 96K CCMRAM_LEN = 32K endif From b06c252a33a33ccc1e05764283aaf4020da72bf5 Mon Sep 17 00:00:00 2001 From: Alexandre Abadie Date: Fri, 25 Sep 2020 15:56:43 +0200 Subject: [PATCH 2/6] boards/stm32: add default tim2 config for stm32g4 --- boards/common/stm32/include/cfg_timer_tim2.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/boards/common/stm32/include/cfg_timer_tim2.h b/boards/common/stm32/include/cfg_timer_tim2.h index 6e54e94715..35a440371e 100644 --- a/boards/common/stm32/include/cfg_timer_tim2.h +++ b/boards/common/stm32/include/cfg_timer_tim2.h @@ -37,7 +37,8 @@ static const timer_conf_t timer_config[] = { #else .max = 0xffffffff, #endif -#if defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32WB) +#if defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32WB) || \ + defined(CPU_FAM_STM32G4) .rcc_mask = RCC_APB1ENR1_TIM2EN, #else .rcc_mask = RCC_APB1ENR_TIM2EN, From 4de05b48378ca9f9e3550a4d24017bcfca10b476 Mon Sep 17 00:00:00 2001 From: Alexandre Abadie Date: Fri, 25 Sep 2020 15:56:56 +0200 Subject: [PATCH 3/6] boards/nucleo-g431rb: add initial support --- boards/nucleo-g431rb/Kconfig | 34 +++++++ boards/nucleo-g431rb/Makefile | 4 + boards/nucleo-g431rb/Makefile.dep | 3 + boards/nucleo-g431rb/Makefile.features | 16 +++ boards/nucleo-g431rb/Makefile.include | 2 + boards/nucleo-g431rb/doc.txt | 26 +++++ boards/nucleo-g431rb/include/periph_conf.h | 110 +++++++++++++++++++++ 7 files changed, 195 insertions(+) create mode 100644 boards/nucleo-g431rb/Kconfig create mode 100644 boards/nucleo-g431rb/Makefile create mode 100644 boards/nucleo-g431rb/Makefile.dep create mode 100644 boards/nucleo-g431rb/Makefile.features create mode 100644 boards/nucleo-g431rb/Makefile.include create mode 100644 boards/nucleo-g431rb/doc.txt create mode 100644 boards/nucleo-g431rb/include/periph_conf.h diff --git a/boards/nucleo-g431rb/Kconfig b/boards/nucleo-g431rb/Kconfig new file mode 100644 index 0000000000..6f8e801b62 --- /dev/null +++ b/boards/nucleo-g431rb/Kconfig @@ -0,0 +1,34 @@ +# Copyright (c) 2020 Inria +# +# This file is subject to the terms and conditions of the GNU Lesser +# General Public License v2.1. See the file LICENSE in the top level +# directory for more details. +# + +config BOARD + default "nucleo-g431rb" if BOARD_NUCLEO_G431RB + +config BOARD_NUCLEO_G431RB + bool + default y + select BOARD_COMMON_NUCLEO64 + select CPU_MODEL_STM32G431RB + + # Put defined MCU peripherals here (in alphabetical order) + select HAS_PERIPH_I2C + select HAS_PERIPH_LPUART + select HAS_PERIPH_RTC + select HAS_PERIPH_RTT + select HAS_PERIPH_SPI + select HAS_PERIPH_TIMER + select HAS_PERIPH_UART + + # Put other features for this board (in alphabetical order) + select HAS_RIOTBOOT + + # Clock configuration + select BOARD_HAS_HSE + select BOARD_HAS_LSE + +source "$(RIOTBOARD)/common/stm32/Kconfig.g4" +source "$(RIOTBOARD)/common/nucleo64/Kconfig" diff --git a/boards/nucleo-g431rb/Makefile b/boards/nucleo-g431rb/Makefile new file mode 100644 index 0000000000..4dd17b1d0c --- /dev/null +++ b/boards/nucleo-g431rb/Makefile @@ -0,0 +1,4 @@ +MODULE = board +DIRS = $(RIOTBOARD)/common/nucleo + +include $(RIOTBASE)/Makefile.base diff --git a/boards/nucleo-g431rb/Makefile.dep b/boards/nucleo-g431rb/Makefile.dep new file mode 100644 index 0000000000..f41bf0f86b --- /dev/null +++ b/boards/nucleo-g431rb/Makefile.dep @@ -0,0 +1,3 @@ +FEATURES_REQUIRED += periph_lpuart + +include $(RIOTBOARD)/common/nucleo/Makefile.dep diff --git a/boards/nucleo-g431rb/Makefile.features b/boards/nucleo-g431rb/Makefile.features new file mode 100644 index 0000000000..74514eec21 --- /dev/null +++ b/boards/nucleo-g431rb/Makefile.features @@ -0,0 +1,16 @@ +CPU = stm32 +CPU_MODEL = stm32g431rb + +# Put defined MCU peripherals here (in alphabetical order) +FEATURES_PROVIDED += periph_i2c +FEATURES_PROVIDED += periph_rtc +FEATURES_PROVIDED += periph_rtt +FEATURES_PROVIDED += periph_spi +FEATURES_PROVIDED += periph_timer +FEATURES_PROVIDED += periph_uart periph_lpuart + +# Put other features for this board (in alphabetical order) +FEATURES_PROVIDED += riotboot + +# load the common Makefile.features for Nucleo boards +include $(RIOTBOARD)/common/nucleo64/Makefile.features diff --git a/boards/nucleo-g431rb/Makefile.include b/boards/nucleo-g431rb/Makefile.include new file mode 100644 index 0000000000..8db8eaed90 --- /dev/null +++ b/boards/nucleo-g431rb/Makefile.include @@ -0,0 +1,2 @@ +# load the common Makefile.include for Nucleo boards +include $(RIOTBOARD)/common/nucleo64/Makefile.include diff --git a/boards/nucleo-g431rb/doc.txt b/boards/nucleo-g431rb/doc.txt new file mode 100644 index 0000000000..33ea658591 --- /dev/null +++ b/boards/nucleo-g431rb/doc.txt @@ -0,0 +1,26 @@ +/** +@defgroup boards_nucleo-g431rb STM32 Nucleo-G431RB +@ingroup boards_common_nucleo64 +@brief Support for the STM32 Nucleo-G431RB + +## Flashing the device + +The ST Nucleo-G431RB board includes an on-board ST-LINK V3 programmer. The +easiest way to program the board is to use OpenOCD. Once you have installed +OpenOCD (look [here](https://github.com/RIOT-OS/RIOT/wiki/OpenOCD) for +installation instructions), you can flash the board simply by typing + +``` +make BOARD=nucleo-g431rb flash +``` +and debug via GDB by simply typing +``` +make BOARD=nucleo-g431rb debug +``` + +## Supported Toolchains + +For using the ST Nucleo-G431RB board we recommend the usage of the +[GNU Tools for ARM Embedded Processors](https://launchpad.net/gcc-arm-embedded) +toolchain. + */ diff --git a/boards/nucleo-g431rb/include/periph_conf.h b/boards/nucleo-g431rb/include/periph_conf.h new file mode 100644 index 0000000000..6f91a68d66 --- /dev/null +++ b/boards/nucleo-g431rb/include/periph_conf.h @@ -0,0 +1,110 @@ +/* + * Copyright (C) 2020 Inria + * + * This file is subject to the terms and conditions of the GNU Lesser + * General Public License v2.1. See the file LICENSE in the top level + * directory for more details. + */ + +/** + * @ingroup boards_nucleo-g431rb + * @{ + * + * @file + * @brief Peripheral MCU configuration for the nucleo-g431rb board + * + * @author Alexandre Abadie + */ + +#ifndef PERIPH_CONF_H +#define PERIPH_CONF_H + +/* Add specific clock configuration (HSE, LSE) for this board here */ +#ifndef CONFIG_BOARD_HAS_LSE +#define CONFIG_BOARD_HAS_LSE (1) +#endif +/* This board provides a 24MHz HSE oscillator */ +#ifndef CONFIG_BOARD_HAS_HSE +#define CONFIG_BOARD_HAS_HSE (1) +#endif +/* By default, configure a 170MHz SYSCLK with PLL using HSE as input clock */ +#ifndef CONFIG_CLOCK_PLL_M +#define CONFIG_CLOCK_PLL_M (6) +#endif + +#include "periph_cpu.h" +#include "g4/cfg_clock_default.h" +#include "cfg_i2c1_pb8_pb9.h" +#include "cfg_rtt_default.h" +#include "cfg_timer_tim2.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @name UART configuration + * @{ + */ +static const uart_conf_t uart_config[] = { + { + .dev = LPUART1, + .rcc_mask = RCC_APB1ENR2_LPUART1EN, + .rx_pin = GPIO_PIN(PORT_A, 3), + .tx_pin = GPIO_PIN(PORT_A, 2), + .rx_af = GPIO_AF12, + .tx_af = GPIO_AF12, + .bus = APB12, + .irqn = LPUART1_IRQn, + .type = STM32_LPUART, + .clk_src = 0, /* Use APB clock */ + }, + { /* Connected to Arduino D0/D1 */ + .dev = USART1, + .rcc_mask = RCC_APB2ENR_USART1EN, + .rx_pin = GPIO_PIN(PORT_C, 5), + .tx_pin = GPIO_PIN(PORT_C, 4), + .rx_af = GPIO_AF7, + .tx_af = GPIO_AF7, + .bus = APB2, + .irqn = USART1_IRQn, + .type = STM32_USART, + .clk_src = 0, /* Use APB clock */ + }, +}; + +#define UART_0_ISR (isr_lpuart1) +#define UART_1_ISR (isr_usart1) + +#define UART_NUMOF ARRAY_SIZE(uart_config) +/** @} */ + +/** + * @name SPI configuration + * @{ + */ +static const spi_conf_t spi_config[] = { + { + .dev = SPI1, + .mosi_pin = GPIO_PIN(PORT_A, 7), /* Arduino D11 */ + .miso_pin = GPIO_PIN(PORT_A, 6), /* Arduino D12 */ + .sclk_pin = GPIO_PIN(PORT_A, 5), /* Arduino D13 */ + .cs_pin = GPIO_UNDEF, + .mosi_af = GPIO_AF5, + .miso_af = GPIO_AF5, + .sclk_af = GPIO_AF5, + .cs_af = GPIO_AF5, + .rccmask = RCC_APB2ENR_SPI1EN, + .apbbus = APB2, + }, +}; + +#define SPI_NUMOF ARRAY_SIZE(spi_config) +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif /* PERIPH_CONF_H */ +/** @} */ From 0eb5c8150112b91e0ff835da3502fa178b2268d1 Mon Sep 17 00:00:00 2001 From: Alexandre Abadie Date: Fri, 25 Sep 2020 16:16:26 +0200 Subject: [PATCH 4/6] boards/nucleo64: adapt user button for nucleo-g431rb --- boards/common/nucleo64/include/board.h | 3 ++- boards/common/nucleo64/include/gpio_params.h | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/boards/common/nucleo64/include/board.h b/boards/common/nucleo64/include/board.h index c110d860fb..4baf9db12a 100644 --- a/boards/common/nucleo64/include/board.h +++ b/boards/common/nucleo64/include/board.h @@ -54,7 +54,8 @@ extern "C" { * @{ */ #define BTN0_PIN GPIO_PIN(PORT_C, 13) -#if defined(CPU_MODEL_STM32L433RC) || defined(CPU_MODEL_STM32G474RE) +#if defined(CPU_MODEL_STM32L433RC) || defined(CPU_MODEL_STM32G474RE) || \ + defined(CPU_MODEL_STM32G431RB) #define BTN0_MODE GPIO_IN_PD #else #define BTN0_MODE GPIO_IN_PU diff --git a/boards/common/nucleo64/include/gpio_params.h b/boards/common/nucleo64/include/gpio_params.h index bcb1dedafd..6ccf295497 100644 --- a/boards/common/nucleo64/include/gpio_params.h +++ b/boards/common/nucleo64/include/gpio_params.h @@ -43,7 +43,8 @@ static const saul_gpio_params_t saul_gpio_params[] = .name = "Button(B1 User)", .pin = BTN0_PIN, .mode = BTN0_MODE, -#if !defined(CPU_MODEL_STM32L433RC) && !defined(CPU_MODEL_STM32G474RE) +#if !defined(CPU_MODEL_STM32L433RC) && !defined(CPU_MODEL_STM32G474RE) && \ + !defined(CPU_MODEL_STM32G431RB) .flags = SAUL_GPIO_INVERTED #endif }, From f92b0fdb40e44ccffc80b271cbd55937d6a3159b Mon Sep 17 00:00:00 2001 From: Alexandre Abadie Date: Fri, 25 Sep 2020 17:57:40 +0200 Subject: [PATCH 5/6] tests: exclude nucleo-g431rb where it doesn't fit --- tests/pkg_utensor/Makefile.ci | 1 + tests/unittests/Makefile.ci | 1 + 2 files changed, 2 insertions(+) diff --git a/tests/pkg_utensor/Makefile.ci b/tests/pkg_utensor/Makefile.ci index a96501e8ce..7a38991b89 100644 --- a/tests/pkg_utensor/Makefile.ci +++ b/tests/pkg_utensor/Makefile.ci @@ -24,6 +24,7 @@ BOARD_INSUFFICIENT_MEMORY := \ nucleo-f410rb \ nucleo-g070rb \ nucleo-g071rb \ + nucleo-g431rb \ nucleo-l031k6 \ nucleo-l053r8 \ nucleo-l412kb \ diff --git a/tests/unittests/Makefile.ci b/tests/unittests/Makefile.ci index c92d02135e..5ad8f40dbf 100644 --- a/tests/unittests/Makefile.ci +++ b/tests/unittests/Makefile.ci @@ -59,6 +59,7 @@ BOARD_INSUFFICIENT_MEMORY := \ nucleo-f410rb \ nucleo-g070rb \ nucleo-g071rb \ + nucleo-g431rb \ nucleo-l031k6 \ nucleo-l053r8 \ nucleo-l073rz \ From a3cf77986617f9d01ed1e31e050174a51063cfc2 Mon Sep 17 00:00:00 2001 From: Alexandre Abadie Date: Tue, 29 Sep 2020 14:09:47 +0200 Subject: [PATCH 6/6] examples: exclude nucleo-g431rb where it doesn't fit --- examples/javascript/Makefile.ci | 1 + examples/lua_REPL/Makefile.ci | 1 + examples/lua_basic/Makefile.ci | 1 + examples/suit_update/Makefile.ci | 1 + 4 files changed, 4 insertions(+) diff --git a/examples/javascript/Makefile.ci b/examples/javascript/Makefile.ci index dacda500f9..d7c5d3ee61 100644 --- a/examples/javascript/Makefile.ci +++ b/examples/javascript/Makefile.ci @@ -32,6 +32,7 @@ BOARD_INSUFFICIENT_MEMORY := \ nucleo-f410rb \ nucleo-g070rb \ nucleo-g071rb \ + nucleo-g431rb \ nucleo-l031k6 \ nucleo-l053r8 \ nucleo-l073rz \ diff --git a/examples/lua_REPL/Makefile.ci b/examples/lua_REPL/Makefile.ci index 9e4e597196..ad5db48f16 100644 --- a/examples/lua_REPL/Makefile.ci +++ b/examples/lua_REPL/Makefile.ci @@ -48,6 +48,7 @@ BOARD_INSUFFICIENT_MEMORY := \ nucleo-f410rb \ nucleo-g070rb \ nucleo-g071rb \ + nucleo-g431rb \ nucleo-l031k6 \ nucleo-l053r8 \ nucleo-l073rz \ diff --git a/examples/lua_basic/Makefile.ci b/examples/lua_basic/Makefile.ci index f68389c1a4..4ec5a19c04 100644 --- a/examples/lua_basic/Makefile.ci +++ b/examples/lua_basic/Makefile.ci @@ -25,6 +25,7 @@ BOARD_INSUFFICIENT_MEMORY := \ nucleo-f410rb \ nucleo-g070rb \ nucleo-g071rb \ + nucleo-g431rb \ nucleo-l031k6 \ nucleo-l053r8 \ nucleo-l412kb \ diff --git a/examples/suit_update/Makefile.ci b/examples/suit_update/Makefile.ci index d08f193281..d885dde802 100644 --- a/examples/suit_update/Makefile.ci +++ b/examples/suit_update/Makefile.ci @@ -17,6 +17,7 @@ BOARD_INSUFFICIENT_MEMORY := \ nucleo-f334r8 \ nucleo-g070rb \ nucleo-g071rb \ + nucleo-g431rb \ nucleo-l031k6 \ nucleo-l053r8 \ nucleo-l073rz \