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boards: add basic support for b-l496g-cell02

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Alexandre Abadie 2019-06-28 11:31:13 +02:00
parent 1f5761ccfa
commit d1fef4803e
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3
boards/p-l496g-cell02/Makefile Normal file
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MODULE = board
include $(RIOTBASE)/Makefile.base

3
boards/p-l496g-cell02/Makefile.dep Normal file
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ifneq (,$(filter saul_default,$(USEMODULE)))
USEMODULE += saul_gpio
endif

10
boards/p-l496g-cell02/Makefile.features Normal file
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# Put defined MCU peripherals here (in alphabetical order)
FEATURES_PROVIDED += periph_i2c
FEATURES_PROVIDED += periph_lpuart
FEATURES_PROVIDED += periph_rtc
FEATURES_PROVIDED += periph_rtt
FEATURES_PROVIDED += periph_spi
FEATURES_PROVIDED += periph_timer
FEATURES_PROVIDED += periph_uart
include $(RIOTCPU)/stm32l4/Makefile.features

18
boards/p-l496g-cell02/Makefile.include Normal file
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# the cpu to build for
export CPU = stm32l4
export CPU_MODEL = stm32l496ag
# we use shared STM32 configuration snippets
INCLUDES += -I$(RIOTBOARD)/common/stm32/include
# define the default port depending on the host OS
PORT_LINUX ?= /dev/ttyACM0
PORT_DARWIN ?= $(firstword $(sort $(wildcard /dev/tty.usbmodem*)))
# setup serial terminal
include $(RIOTMAKE)/tools/serial.inc.mk
DEBUG_ADAPTER ?= stlink
# this board uses openocd
include $(RIOTMAKE)/tools/openocd.inc.mk

32
boards/p-l496g-cell02/board.c Normal file
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/*
* Copyright (C) 2019 Inria
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @ingroup boards_p-l496g-cell02
* @{
*
* @file
* @brief Board specific implementations for the P-L496G-CELL02 board
*
* @author Alexandre Abadie <alexandre.abadie@inria.fr>
*
* @}
*/
#include "board.h"
#include "periph/gpio.h"
void board_init(void)
{
/* initialize LEDs */
gpio_init(LED0_PIN, GPIO_OUT);
gpio_init(LED1_PIN, GPIO_OUT);
/* initialize the CPU */
cpu_init();
}

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boards/p-l496g-cell02/doc.txt Normal file
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/**
* @defgroup boards_p-l496g-cell02 ST P-L496G-CELL02
* @ingroup boards
* @brief Support for the ST P-L496G-CELL02 board
## Overview
The ST [P-L496G-CELL02](https://www.st.com/en/evaluation-tools/p-l496g-cell02.html)
is an evaluation board supporting a ARM Cortex-M4 STM32L496AG microcontroller
with 320Kb of RAM and 1Mb of ROM Flash.
## Flashing the device
The P-L496G-CELL02 board includes an on-board ST-LINK programmer and can be
flashed using OpenOCD.
To flash this board, just use the following command:
```
make BOARD=p-l496g-cell02 flash -C examples/hello-world
```
### STDIO
STDIO is available via the ST-Link programmer.
Use the `term` targed to open a terminal:
make BOARD=p-l496g-cell02 -C examples/hello-world term
*/

79
boards/p-l496g-cell02/include/board.h Normal file
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/*
* Copyright (C) 2019 Inria
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @ingroup boards_p-l496g-cell02
* @{
*
* @file
* @brief Board specific definitions for the P-L496G-CELL02 board
*
* @author Alexandre Abadie <alexandre.abadie@inria.fr>
*/
#ifndef BOARD_H
#define BOARD_H
#include <stdint.h>
#include "cpu.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @name LED pin definitions and handlers
* @{
*/
#define LED0_PIN GPIO_PIN(PORT_A, 5)
#define LED0_MASK (1 << 5)
#define LED0_ON (GPIOA->BSRR = LED0_MASK)
#define LED0_OFF (GPIOA->BSRR = (LED0_MASK << 16))
#define LED0_TOGGLE (GPIOA->ODR ^= LED0_MASK)
#define LED1_PIN GPIO_PIN(PORT_B, 13)
#define LED1_MASK (1 << 13)
#define LED1_ON (GPIOB->BSRR = LED1_MASK)
#define LED1_OFF (GPIOB->BSRR = (LED1_MASK << 16))
#define LED1_TOGGLE (GPIOB->ODR ^= LED1_MASK)
/** @} */
/**
* @name Joystick buttons
* @{
*/
#define BTN0_PIN GPIO_PIN(PORT_C, 13) /**< Center button pin */
#define BTN0_MODE GPIO_IN_PD /**< Center button mode */
#define BTN1_PIN GPIO_PIN(PORT_I, 9) /**< Left button pin */
#define BTN1_MODE GPIO_IN_PD /**< Left button mode */
#define BTN2_PIN GPIO_PIN(PORT_I, 10) /**< Down button pin */
#define BTN2_MODE GPIO_IN_PD /**< Down button mode */
#define BTN3_PIN GPIO_PIN(PORT_F, 11) /**< Right button pin */
#define BTN3_MODE GPIO_IN_PD /**< Right button mode */
#define BTN4_PIN GPIO_PIN(PORT_I, 8) /**< Up button pin */
#define BTN4_MODE GPIO_IN_PD /**< Up button mode */
/** @} */
/**
* @brief Initialize board specific hardware, including clock, LEDs and std-IO
*/
void board_init(void);
#ifdef __cplusplus
}
#endif
#endif /* BOARD_H */
/** @} */

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boards/p-l496g-cell02/include/gpio_params.h Normal file
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/*
* Copyright (C) 2019 Inria
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @ingroup boards_p-l496g-cell02
* @{
*
* @file
* @brief Board specific configuration of direct mapped GPIOs
*
* @author Alexandre Abadie <alexandre.abadie@inria.fr>
*/
#ifndef GPIO_PARAMS_H
#define GPIO_PARAMS_H
#include "board.h"
#include "saul/periph.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief GPIO pin configuration
*/
static const saul_gpio_params_t saul_gpio_params[] =
{
{
.name = "LD3",
.pin = LED0_PIN,
.mode = GPIO_OUT,
},
{
.name = "LD1",
.pin = LED1_PIN,
.mode = GPIO_OUT,
.flags = (SAUL_GPIO_INVERTED | SAUL_GPIO_INIT_CLEAR),
},
{
.name = "Joystick (Center)",
.pin = BTN0_PIN,
.mode = BTN0_MODE
},
{
.name = "Joystick (Left)",
.pin = BTN1_PIN,
.mode = BTN1_MODE
},
{
.name = "Joystick (Down)",
.pin = BTN2_PIN,
.mode = BTN2_MODE
},
{
.name = "Joystick (Right)",
.pin = BTN3_PIN,
.mode = BTN3_MODE
},
{
.name = "Joystick (Up)",
.pin = BTN4_PIN,
.mode = BTN4_MODE
},
};
#ifdef __cplusplus
}
#endif
#endif /* GPIO_PARAMS_H */
/** @} */

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boards/p-l496g-cell02/include/periph_conf.h Normal file
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/*
* Copyright (C) 2019 Inria
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @ingroup boards_p-l496g-cell02
* @{
*
* @file
* @brief Peripheral MCU configuration for the P-L496G-CELL02 board
*
* @author Alexandre Abadie <alexandre.abadie@inria.fr>
*/
#ifndef PERIPH_CONF_H
#define PERIPH_CONF_H
#include "periph_cpu.h"
#include "cfg_rtt_default.h"
#include "cfg_timer_tim2.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @name Clock system configuration
* @{
*/
/* 0: no external high speed crystal available
* else: actual crystal frequency [in Hz] */
#define CLOCK_HSE (0)
/* 0: no external low speed crystal available,
* 1: external crystal available (always 32.768kHz) */
#define CLOCK_LSE (1)
/* 0: enable MSI only if HSE isn't available
* 1: always enable MSI (e.g. if USB or RNG is used)*/
#define CLOCK_MSI_ENABLE (1)
/* 0: disable Hardware auto calibration with LSE
* 1: enable Hardware auto calibration with LSE (PLL-mode)*/
#define CLOCK_MSI_LSE_PLL (1)
/* give the target core clock (HCLK) frequency [in Hz], maximum: 80MHz */
#define CLOCK_CORECLOCK (80000000U)
/* PLL configuration: make sure your values are legit!
*
* compute by: CORECLOCK = (((PLL_IN / M) * N) / R)
* with:
* PLL_IN: input clock, HSE or MSI @ 48MHz
* M: pre-divider, allowed range: [1:8]
* N: multiplier, allowed range: [8:86]
* R: post-divider, allowed range: [2,4,6,8]
*
* Also the following constraints need to be met:
* (PLL_IN / M) -> [4MHz:16MHz]
* (PLL_IN / M) * N -> [64MHz:344MHz]
* CORECLOCK -> 80MHz MAX!
*/
#define CLOCK_PLL_M (6)
#define CLOCK_PLL_N (20)
#define CLOCK_PLL_R (2)
/* peripheral clock setup */
#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV4
#define CLOCK_APB1 (CLOCK_CORECLOCK / 4)
#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV2
#define CLOCK_APB2 (CLOCK_CORECLOCK / 2)
/** @} */
/**
* @name UART configuration
* @{
*/
static const uart_conf_t uart_config[] = {
{
.dev = USART2,
.rcc_mask = RCC_APB1ENR1_USART2EN,
.rx_pin = GPIO_PIN(PORT_D, 6),
.tx_pin = GPIO_PIN(PORT_A, 2),
.rx_af = GPIO_AF7,
.tx_af = GPIO_AF7,
.bus = APB1,
.irqn = USART2_IRQn,
#ifdef MODULE_STM32_PERIPH_UART_HW_FC
.cts_pin = GPIO_UNDEF,
.rts_pin = GPIO_UNDEF,
.cts_af = GPIO_AF7,
.rts_af = GPIO_AF7,
#endif
.type = STM32_USART,
.clk_src = 0, /* Use APB clock */
},
{ /* Arduino pinout RX/TX pins on D0/D1 */
.dev = LPUART1,
.rcc_mask = RCC_APB1ENR2_LPUART1EN,
.rx_pin = GPIO_PIN(PORT_G, 8),
.tx_pin = GPIO_PIN(PORT_G, 7),
.rx_af = GPIO_AF8,
.tx_af = GPIO_AF8,
.bus = APB12,
.irqn = LPUART1_IRQn,
#ifdef MODULE_STM32_PERIPH_UART_HW_FC
.cts_pin = GPIO_UNDEF,
.rts_pin = GPIO_UNDEF,
.cts_af = GPIO_AF7,
.rts_af = GPIO_AF7,
#endif
.type = STM32_LPUART,
.clk_src = 0,
},
{ /* STMod+/PMOD connectors */
.dev = USART1,
.rcc_mask = RCC_APB2ENR_USART1EN,
.rx_pin = GPIO_PIN(PORT_B, 6),
.tx_pin = GPIO_PIN(PORT_G, 10),
.rx_af = GPIO_AF7,
.tx_af = GPIO_AF7,
.bus = APB2,
.irqn = USART1_IRQn,
#ifdef MODULE_STM32_PERIPH_UART_HW_FC
.cts_pin = GPIO_PIN(PORT_G, 11),
.rts_pin = GPIO_PIN(PORT_G, 12),
.cts_af = GPIO_AF7,
.rts_af = GPIO_AF7,
#endif
.type = STM32_USART,
.clk_src = 0, /* Use APB clock */
}
};
#define UART_0_ISR (isr_usart2)
#define UART_1_ISR (isr_lpuart1)
#define UART_2_ISR (isr_usart1)
#define UART_NUMOF ARRAY_SIZE(uart_config)
/** @} */
/**
* @name I2C configuration
* @{
*/
static const i2c_conf_t i2c_config[] = {
{
.dev = I2C1,
.speed = I2C_SPEED_NORMAL,
.scl_pin = GPIO_PIN(PORT_B, 8),
.sda_pin = GPIO_PIN(PORT_B, 7),
.scl_af = GPIO_AF4,
.sda_af = GPIO_AF4,
.bus = APB1,
.rcc_mask = RCC_APB1ENR1_I2C1EN,
.irqn = I2C1_ER_IRQn
},
};
#define I2C_0_ISR isr_i2c1_er
#define I2C_NUMOF ARRAY_SIZE(i2c_config)
/** @} */
/**
* @name SPI configuration
*
* @note The spi_divtable is auto-generated from
* `cpu/stm32_common/dist/spi_divtable/spi_divtable.c`
* @{
*/
static const uint8_t spi_divtable[2][5] = {
{ /* for APB1 @ 20000000Hz */
7, /* -> 78125Hz */
5, /* -> 312500Hz */
3, /* -> 1250000Hz */
1, /* -> 5000000Hz */
0 /* -> 10000000Hz */
},
{ /* for APB2 @ 40000000Hz */
7, /* -> 156250Hz */
6, /* -> 312500Hz */
4, /* -> 1250000Hz */
2, /* -> 5000000Hz */
1 /* -> 10000000Hz */
}
};
static const spi_conf_t spi_config[] = {
{
.dev = SPI1,
.mosi_pin = GPIO_PIN(PORT_B, 5),
.miso_pin = GPIO_PIN(PORT_B, 4),
.sclk_pin = GPIO_PIN(PORT_A, 5),
.cs_pin = GPIO_UNDEF,
.af = GPIO_AF5,
.rccmask = RCC_APB2ENR_SPI1EN,
.apbbus = APB2
}
};
#define SPI_NUMOF ARRAY_SIZE(spi_config)
/** @} */
#ifdef __cplusplus
}
#endif
#endif /* PERIPH_CONF_H */
/** @} */