diff --git a/cpu/atmega2560/include/periph_cpu.h b/cpu/atmega2560/include/periph_cpu.h index 5d6cd4746f..9d94934bb8 100644 --- a/cpu/atmega2560/include/periph_cpu.h +++ b/cpu/atmega2560/include/periph_cpu.h @@ -1,5 +1,6 @@ /* * Copyright (C) 2015 HAW Hamburg + * 2016 Freie Universität Berlin * * This file is subject to the terms and conditions of the GNU Lesser * General Public License v2.1. See the file LICENSE in the top level @@ -14,14 +15,12 @@ * @brief CPU specific definitions for internal peripheral handling * * @author René Herthel + * @author Hauke Petersen */ #ifndef PERIPH_CPU_H_ #define PERIPH_CPU_H_ -#include "periph/dev_enums.h" -#include - #ifdef __cplusplus extern "C" { #endif @@ -48,6 +47,54 @@ enum { PORT_L = 10 /**< port L */ }; +/** + * @brief SPI mode select macro + * + * The polarity is determined by bit 3 in the configuration register, the phase + * by bit 2. + */ +#define SPI_MODE_SEL(pol, pha) ((pol << 3) | (pha << 2)) + +/** + * @brief Override the SPI mode values + * + * As the mode is set in bit 3 and 2 of the configuration register, we put the + * correct configuration there + * @{ + */ +#define HAVE_SPI_CONF_T +typedef enum { + SPI_CONF_FIRST_RISING = SPI_MODE_SEL(0, 0), /**< mode 0 */ + SPI_CONF_SECOND_RISING = SPI_MODE_SEL(0, 1), /**< mode 1 */ + SPI_CONF_FIRST_FALLING = SPI_MODE_SEL(1, 0), /**< mode 2 */ + SPI_CONF_SECOND_FALLING = SPI_MODE_SEL(1, 1) /**< mode 3 */ +} spi_conf_t; +/** @} */ + +/** + * @brief SPI speed selection macro + * + * We encode the speed in bits 2, 1, and 0, where bit0 and bit1 hold the SPCR + * prescaler bits, while bit2 holds the SPI2X bit. + */ +#define SPI_SPEED_SEL(s2x, pr1, pr0) ((s2x << 2) | (pr1 << 1) | pr0) + +/** + * @brief Override SPI speed values + * + * We assume a master clock speed of 16MHz here. + * @{ + */ +#define HAVE_SPI_SPEED_T +typedef enum { + SPI_SPEED_100KHZ = SPI_SPEED_SEL(0, 1, 1), /**< 16/128 -> 125KHz */ + SPI_SPEED_400KHZ = SPI_SPEED_SEL(1, 1, 0), /**< 16/32 -> 500KHz */ + SPI_SPEED_1MHZ = SPI_SPEED_SEL(0, 0, 1), /**< 16/16 -> 1MHz */ + SPI_SPEED_5MHZ = SPI_SPEED_SEL(0, 0, 0), /**< 16/4 -> 4MHz */ + SPI_SPEED_10MHZ = SPI_SPEED_SEL(1, 0, 0) /**< 16/2 -> 8MHz */ +} spi_speed_t; +/** @} */ + #ifdef __cplusplus } #endif diff --git a/cpu/atmega2560/periph/spi.c b/cpu/atmega2560/periph/spi.c new file mode 100644 index 0000000000..17f1e85b7d --- /dev/null +++ b/cpu/atmega2560/periph/spi.c @@ -0,0 +1,145 @@ +/* + * Copyright (C) 2015 Daniel Amkaer Sorensen + * 2016 Freie Universität Berlin + * + * This file is subject to the terms and conditions of the GNU Lesser + * General Public License v2.1. See the file LICENSE in the top level + * directory for more details. + */ + +/** + * @ingroup cpu_atmega2560 + * @{ + * + * @file + * @brief Low-level SPI driver implementation + * + * @author Daniel Amkaer Sorensen + * @author Hauke Petersen + * + * @} + */ + +#include "cpu.h" +#include "mutex.h" +#include "periph/spi.h" + +/* guard this file in case no SPI device is defined */ +#if SPI_NUMOF + +/** + * @brief Extract BR0, BR1 and SPI2X bits from speed value + * @{ + */ +#define SPEED_MASK (0x3) +#define S2X_SHIFT (2) +/** @} */ + +static mutex_t lock = MUTEX_INIT; + +int spi_init_master(spi_t dev, spi_conf_t conf, spi_speed_t speed) +{ + /* make sure device is valid (there is only one...) */ + if (dev != 0) { + return -1; + } + + /* the pin configuration for this CPU is fixed: + * - PB3: MISO (configure as input - done automatically) + * - PB2: MOSI (configure as output) + * - PB1: SCK (configure as output) + * - PB0: SS (configure as output, but unused) + * + * The SS pin must be configured as output for the SPI device to work as + * master correctly, though we do not use it for now (as we handle the chip + * select externally for now) + */ + DDRB |= ((1 << DDB2) | (1 << DDB1) | (1 << DDB0)); + + /* make sure the SPI is not powered off */ + PRR0 &= ~(1 << PRSPI); + + /* configure as master, with given mode and clock */ + SPSR = (speed >> S2X_SHIFT); + SPCR = ((1 << SPE) | (1 << MSTR) | conf | (speed & SPEED_MASK)); + + /* clear interrupt flag */ + (void)SPSR; + (void)SPDR; + + return 0; +} + +int spi_acquire(spi_t dev) +{ + mutex_lock(&lock); + return 0; +} + +int spi_release(spi_t dev) +{ + mutex_unlock(&lock); + return 0; +} + +int spi_init_slave(spi_t dev, spi_conf_t conf, char (*cb)(char data)) +{ + (void) dev; + (void) conf; + (void) cb; + + /* not implemented */ + return -1; +} + +void spi_transmission_begin(spi_t dev, char reset_val) +{ + (void)dev; + (void)reset_val; + + /* not implemented */ +} + +int spi_transfer_byte(spi_t dev, char out, char *in) +{ + return spi_transfer_bytes(dev, &out, in, 1); +} + +int spi_transfer_bytes(spi_t dev, char *out, char *in, unsigned int length) +{ + for (unsigned int i = 0; i < length; i++) { + char tmp = (out) ? out[i] : 0; + SPDR = tmp; + while (!(SPSR & (1 << SPIF))) {} + tmp = SPDR; + if (in) { + in[i] = tmp; + } + } + + return (int)length; +} + +int spi_transfer_reg(spi_t dev, uint8_t reg, char out, char *in) +{ + spi_transfer_bytes(dev, (char *)®, NULL, 1); + return spi_transfer_bytes(dev, &out, in, 1); +} + +int spi_transfer_regs(spi_t dev, uint8_t reg, char *out, char *in, unsigned int length) +{ + spi_transfer_bytes(dev, (char *)®, NULL, 1); + return spi_transfer_bytes(dev, out, in, length); +} + +void spi_poweron(spi_t dev) +{ + SPCR |= (1 << SPE); +} + +void spi_poweroff(spi_t dev) +{ + SPCR &= ~(1 << SPE); +} + +#endif /* SPI_NUMOF */