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cpu: stm32f3: SPI: force 8bit transfers

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This commit is contained in:
Kaspar Schleiser 2015-03-23 11:10:08 +01:00
parent 333dae4c57
commit cfcd06964a
1 changed files with 21 additions and 11 deletions
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32
cpu/stm32f3/periph/spi.c
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@ -144,8 +144,12 @@ int spi_init_master(spi_t dev, spi_conf_t conf, spi_speed_t speed)
spi[dev]->CR1 |= (speed_divider << 3); /* Define serial clock baud rate. 001 leads to f_PCLK/4 */ spi[dev]->CR1 |= (speed_divider << 3); /* Define serial clock baud rate. 001 leads to f_PCLK/4 */
spi[dev]->CR1 |= (SPI_CR1_MSTR); /* 1: master configuration */ spi[dev]->CR1 |= (SPI_CR1_MSTR); /* 1: master configuration */
spi[dev]->CR1 |= (conf); spi[dev]->CR1 |= (conf);
spi[dev]->CR2 |= SPI_CR2_FRXTH; /* set FIFO reception threshold to 8bit (default: 16bit) */
/* enable SPI */ /* enable SPI */
spi[dev]->CR1 |= (SPI_CR1_SPE); spi[dev]->CR1 |= (SPI_CR1_SPE);
return 0; return 0;
} }
@ -303,20 +307,26 @@ int spi_release(spi_t dev)
int spi_transfer_byte(spi_t dev, char out, char *in) int spi_transfer_byte(spi_t dev, char out, char *in)
{ {
if (dev >= SPI_NUMOF) { char tmp;
return -1;
}
while (!(spi[dev]->SR & SPI_SR_TXE)); /* recast to uint_8 to force 8bit access */
spi[dev]->DR = out; volatile uint8_t *DR = (volatile uint8_t*) &spi[dev]->DR;
while (!(spi[dev]->SR & SPI_SR_RXNE)); /* wait for an eventually previous byte to be readily transferred */
while(!(spi[dev]->SR & SPI_SR_TXE));
if (in != NULL) { /* put next byte into the output register */
*in = spi[dev]->DR; *DR = out;
}
else { /* wait until the current byte was successfully transferred */
spi[dev]->DR; while(!(spi[dev]->SR & SPI_SR_RXNE) );
/* read response byte to reset flags */
tmp = *DR;
/* 'return' response byte if wished for */
if (in) {
*in = tmp;
} }
return 1; return 1;