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Merge pull request #3525 from kaspar030/switch_to_xtimer

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switch to xtimer
This commit is contained in:
Kaspar Schleiser 2015-09-16 13:06:14 +02:00
commit cca167e77c
233 changed files with 1065 additions and 3868 deletions
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75
Makefile.dep
View File

@ -1,7 +1,19 @@
ifneq (,$(filter libcoap,$(USEPKG)))
USEMODULE += pnet
endif
ifneq (,$(filter pnet,$(USEMODULE)))
USEMODULE += vtimer
endif
ifneq (,$(filter gnrc_%,$(filter-out gnrc_netapi gnrc_netreg gnrc_netif% gnrc_pktbuf,$(USEMODULE))))
USEMODULE += gnrc
endif
ifneq (,$(filter schedstatistics,$(USEMODULE)))
USEMODULE += xtimer
endif
ifneq (,$(filter gnrc_netif_default,$(USEMODULE)))
USEMODULE += gnrc_netif
endif
@ -9,6 +21,7 @@ endif
ifneq (,$(filter at86rf2%,$(USEMODULE)))
USEMODULE += at86rf2xx
USEMODULE += ieee802154
USEMODULE += xtimer
endif
ifneq (,$(filter kw2xrf,$(USEMODULE)))
@ -17,6 +30,7 @@ endif
ifneq (,$(filter xbee,$(USEMODULE)))
USEMODULE += ieee802154
USEMODULE += xtimer
endif
ifneq (,$(filter gnrc_zep,$(USEMODULE)))
@ -31,7 +45,11 @@ ifneq (,$(filter gnrc_rpl,$(USEMODULE)))
USEMODULE += fib
USEMODULE += gnrc_ipv6_router_default
USEMODULE += trickle
USEMODULE += vtimer
USEMODULE += xtimer
endif
ifneq (,$(filter trickle,$(USEMODULE)))
USEMODULE += xtimer
endif
ifneq (,$(filter ieee802154,$(USEMODULE)))
@ -253,6 +271,7 @@ ifneq (,$(filter cbor,$(USEMODULE)))
endif
ifneq (,$(filter vtimer,$(USEMODULE)))
USEMODULE += xtimer
USEMODULE += timex
endif
@ -272,8 +291,7 @@ endif
ifneq (,$(filter fib,$(USEMODULE)))
USEMODULE += universal_address
USEMODULE += timex
USEMODULE += vtimer
USEMODULE += xtimer
USEMODULE += net_help
endif
@ -320,14 +338,59 @@ ifneq (,$(filter gnrc_netdev2,$(USEMODULE)))
endif
ifneq (,$(filter hih6130,$(USEMODULE)))
USEMODULE += vtimer
USEMODULE += xtimer
endif
ifneq (,$(filter encx24j600,$(USEMODULE)))
USEMODULE += timex
USEMODULE += vtimer
USEMODULE += xtimer
endif
ifneq (,$(filter srf02,$(USEMODULE)))
USEMODULE += xtimer
endif
ifneq (,$(filter dht,$(USEMODULE)))
USEMODULE += xtimer
endif
ifneq (,$(filter lm75a,$(USEMODULE)))
USEMODULE += xtimer
endif
ifneq (,$(filter mpu9150,$(USEMODULE)))
USEMODULE += xtimer
endif
ifneq (,$(filter sht11,$(USEMODULE)))
USEMODULE += xtimer
endif
ifneq (,$(filter srf02,$(USEMODULE)))
USEMODULE += xtimer
endif
ifneq (,$(filter pcd8544,$(USEMODULE)))
USEMODULE += xtimer
endif
ifneq (,$(filter nvram_spi,$(USEMODULE)))
USEMODULE += xtimer
endif
ifneq (,$(filter ltc4150,$(USEMODULE)))
USEMODULE += xtimer
endif
ifneq (,$(filter pthread,$(USEMODULE)))
USEMODULE += xtimer
USEMODULE += vtimer
USEMODULE += timex
endif
ifneq (,$(filter schedstatistics,$(USEMODULE)))
USEMODULE += xtimer
endif
ifneq (,$(filter xtimer,$(USEMODULE)))
FEATURES_REQUIRED += periph_timer
endif

1
Makefile.pseudomodules
View File

@ -13,6 +13,7 @@ PSEUDOMODULES += log
PSEUDOMODULES += log_printfnoformat
PSEUDOMODULES += newlib
PSEUDOMODULES += pktqueue
PSEUDOMODULES += schedstatistics
# include variants of the AT86RF2xx drivers as pseudo modules
PSEUDOMODULES += at86rf23%

1
boards/airfy-beacon/Makefile.features
View File

@ -6,4 +6,5 @@ FEATURES_PROVIDED += periph_random
FEATURES_PROVIDED += periph_rtt
FEATURES_PROVIDED += periph_cpuid
FEATURES_PROVIDED += periph_spi
FEATURES_PROVIDED += periph_timer
FEATURES_MCU_GROUP = cortex_m0

16
boards/airfy-beacon/include/board.h
View File

@ -32,6 +32,17 @@
*/
#define F_CPU (16000000UL)
/**
* @brief Xtimer configuration
* @{
*/
#define XTIMER (0)
#define XTIMER_CHAN (0)
#define XTIMER_MASK (0xff000000)
#define XTIMER_SHIFT_ON_COMPARE (2)
#define XTIMER_BACKOFF (40)
/** @} */
/**
* @name Define the boards stdio
* @{
@ -41,11 +52,6 @@
#define STDIO_RX_BUFSIZE (64U)
/** @} */
/**
* @name Assign the hardware timer
*/
#define HW_TIMER TIMER_0
/**
* @name Macros for controlling the on-board LEDs.
* @{

1
boards/arduino-due/Makefile.features
View File

@ -4,4 +4,5 @@ FEATURES_PROVIDED += periph_gpio
FEATURES_PROVIDED += periph_pwm
FEATURES_PROVIDED += periph_spi
FEATURES_PROVIDED += periph_random
FEATURES_PROVIDED += periph_timer
FEATURES_MCU_GROUP = cortex_m3_1

1
boards/arduino-mega2560/Makefile.features
View File

@ -1,3 +1,4 @@
FEATURES_PROVIDED += periph_uart
FEATURES_PROVIDED += periph_gpio
FEATURES_PROVIDED += periph_timer
FEATURES_MCU_GROUP = avr8

8
boards/arduino-mega2560/include/board.h
View File

@ -73,6 +73,14 @@ extern "C" {
#define LED_RED_TOGGLE /* not available */
/** @} */
/**
* @brief xtimer configuration values
* @{
*/
#define XTIMER_SHIFT (2)
#define XTIMER_SHIFT_ON_COMPARE (8)
#define XTIMER_BACKOFF (40)
/** @} */
/**
* @brief Initialize board specific hardware, including clock, LEDs and std-IO

26
boards/avsextrem/drivers/avsextrem-smb380.c
View File

@ -34,7 +34,7 @@
#include "kernel.h"
#include "ssp0-board.h"
#include "smb380-board.h"
#include "hwtimer.h"
#include "xtimer.h"
#include "sched.h"
#include "msg.h"
#include "irq.h"
@ -176,7 +176,7 @@ uint8_t SMB380_init_simple(uint16_t samplerate, uint8_t bandwidth, uint8_t
simple_pid = sched_active_pid;
gpioint_set(0, BIT1, GPIOINT_RISING_EDGE, &SMB380_simple_interrupthandler);
SMB380_softReset();
hwtimer_wait(HWTIMER_TICKS(100000));
xtimer_usleep(100000);
SMB380_disableUpperLimit();
SMB380_disableLowerLimit();
SMB380_setSampleRate(samplerate);
@ -208,7 +208,7 @@ uint8_t SMB380_init(uint8_t (*func)(int16_t *))
//smb380function = SMB380_HystereseFunctionSample; //placeholder
SMB380_softReset();
hwtimer_wait(HWTIMER_TICKS(100000));
xtimer_usleep(100000);
SMB380_disableUpperLimit();
SMB380_disableLowerLimit();
@ -409,7 +409,7 @@ uint8_t writeRingBuff(int16_t *value)
/* measuring temperature dependent internal sample rate of SMB380 */
if (smb380_mode == SMB380_CONTINOUS) {
tickLastSample = hwtimer_now();
tickLastSample = xtimer_now();
tickCurrentSamples++;
}
@ -1039,7 +1039,7 @@ void SMB380_enableNewDataInt(void)
SMB380_ssp_read();
SMB380_Unprepare();
// measuring temperature dependent internal sample rate of SMB380
tickStart = hwtimer_now();
tickStart = xtimer_now();
tickCurrentSamples = 0;
restoreIRQ(cpsr);
}
@ -1198,13 +1198,13 @@ void SMB380_writeOffset(uint16_t *offset, uint8_t EEPROM)
SMB380_ssp_write(SMB380_OFFSET_LSB_GAIN_X + eeoffset, (uint8_t)uReg,
SMB380_WRITE_REGISTER); //write them to image or eeprom
SMB380_ssp_read();
hwtimer_wait(HWTIMER_TICKS(50000));
xtimer_usleep(50000);
uReg = (offset[0] & 0x3FC) >> 2; //get MSB Bits
SMB380_ssp_write(SMB380_OFFSET_MSB_X + eeoffset, (uint8_t)uReg,
SMB380_WRITE_REGISTER); //write them to image or eeprom
SMB380_ssp_read();
hwtimer_wait(HWTIMER_TICKS(50000));
xtimer_usleep(50000);
//y-Axis
uReg = (offset[1] & 0x03) << 6; //get both LSB Bits
@ -1213,13 +1213,13 @@ void SMB380_writeOffset(uint16_t *offset, uint8_t EEPROM)
SMB380_ssp_write(SMB380_OFFSET_LSB_GAIN_Y + eeoffset, (uint8_t)uReg,
SMB380_WRITE_REGISTER); //write them to image or eeprom
SMB380_ssp_read();
hwtimer_wait(HWTIMER_TICKS(50000));
xtimer_usleep(50000);
uReg = (offset[1] & 0x3FC) >> 2; //get MSB Bits
SMB380_ssp_write(SMB380_OFFSET_MSB_Y + eeoffset, (uint8_t)uReg,
SMB380_WRITE_REGISTER); //write them to image or eeprom
SMB380_ssp_read();
hwtimer_wait(HWTIMER_TICKS(50000));
xtimer_usleep(50000);
//z-Axis
uReg = (offset[2] & 0x03) << 6; //get both LSB Bits
@ -1229,13 +1229,13 @@ void SMB380_writeOffset(uint16_t *offset, uint8_t EEPROM)
SMB380_ssp_write(SMB380_OFFSET_LSB_GAIN_Z + eeoffset, (uint8_t)uReg,
SMB380_WRITE_REGISTER); //write them to image or eeprom
SMB380_ssp_read();
hwtimer_wait(HWTIMER_TICKS(50000));
xtimer_usleep(50000);
uReg = (offset[2] & 0x3FC) >> 2; //get MSB Bits
SMB380_ssp_write(SMB380_OFFSET_MSB_Z + eeoffset, (uint8_t)uReg,
SMB380_WRITE_REGISTER); //write them to image or eeprom
SMB380_ssp_read();
hwtimer_wait(HWTIMER_TICKS(50000));
xtimer_usleep(50000);
SMB380_Unprepare();
restoreIRQ(cpsr);
@ -1267,13 +1267,13 @@ void SMB380_writeOffsetTemp(uint16_t *offset, uint8_t EEPROM)
SMB380_ssp_write(SMB380_OFFSET_LSB_GAIN_T + eeoffset, (uint8_t)uReg,
SMB380_WRITE_REGISTER); //write them to image or eeprom
SMB380_ssp_read();
hwtimer_wait(HWTIMER_TICKS(50000));
xtimer_usleep(50000);
uReg = (offset[0] & 0x3FC) >> 2; //get MSB Bits
SMB380_ssp_write(SMB380_OFFSET_MSB_T + eeoffset, (uint8_t)uReg,
SMB380_WRITE_REGISTER); //write them to image or eeprom
SMB380_ssp_read();
hwtimer_wait(HWTIMER_TICKS(50000));
xtimer_usleep(50000);
SMB380_Unprepare();
restoreIRQ(cpsr);

1
boards/avsextrem/drivers/avsextrem-ssp0.c
View File

@ -27,7 +27,6 @@
#include "smb380-board.h"
//#include "mma7455l-board.h"
#include "gpioint.h"
#include "hwtimer.h"
#include <stdio.h>
#include "lpm.h"

1
boards/cc2538dk/Makefile.features
View File

@ -3,4 +3,5 @@ FEATURES_PROVIDED += periph_uart
FEATURES_PROVIDED += periph_gpio
FEATURES_PROVIDED += periph_random
FEATURES_PROVIDED += periph_cpuid
FEATURES_PROVIDED += periph_timer
FEATURES_MCU_GROUP = cortex_m3_1

6
boards/chronos/drivers/buzzer.c
View File

@ -26,9 +26,9 @@
#include <cc430f6137.h>
#include "buzzer.h"
#include "hwtimer.h"
#include "xtimer.h"
void buzzer_beep(uint8_t pitch, uint16_t duration)
void buzzer_beep(uint8_t pitch, uint32_t duration)
{
// Reset TA1R, set up mode, TA1 runs from 32768Hz ACLK
TA1CTL = TACLR | MC_1 | TASSEL__ACLK;
@ -42,7 +42,7 @@ void buzzer_beep(uint8_t pitch, uint16_t duration)
// Allow buzzer PWM output on P2.7
P2SEL |= BIT7;
hwtimer_wait(duration);
xtimer_usleep(duration);
// Stop PWM timer
TA1CTL &= ~(BIT4 | BIT5);

4
boards/chronos/drivers/include/buzzer.h
View File

@ -9,11 +9,13 @@
#ifndef BUZZER_H_
#define BUZZER_H_
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
void buzzer_beep(uint8_t pitch, uint16_t duration);
void buzzer_beep(uint8_t pitch, uint32_t duration);
#ifdef __cplusplus
}

7
boards/chronos/include/board.h
View File

@ -39,14 +39,9 @@ extern "C" {
#define XTIMER (0)
#define XTIMER_CHAN (0)
#define XTIMER_MASK (0xffff0000)
#define XTIMER_SHIFT_ON_COMPARE (4)
/** @} */
/**
* @brief Defines for compatibility with hwtimer
* @deprecated
*/
#define HW_TIMER (0)
/**
* @brief Standard input/output device configuration
*

1
boards/ek-lm4f120xl/Makefile.features
View File

@ -1,4 +1,5 @@
FEATURES_PROVIDED += cpp
FEATURES_PROVIDED += periph_uart
FEATURES_PROVIDED += periph_cpuid
FEATURES_PROVIDED += periph_timer
FEATURES_MCU_GROUP = cortex_m4

1
boards/f4vi1/Makefile.features
View File

@ -1,3 +1,4 @@
FEATURES_PROVIDED += cpp
FEATURES_PROVIDED += periph_uart
FEATURES_PROVIDED += periph_timer
FEATURES_MCU_GROUP = cortex_m4

1
boards/fox/Makefile.features
View File

@ -3,6 +3,7 @@ FEATURES_PROVIDED += periph_uart
FEATURES_PROVIDED += periph_spi
FEATURES_PROVIDED += periph_i2c
FEATURES_PROVIDED += periph_rtt
FEATURES_PROVIDED += periph_timer
FEATURES_PROVIDED += periph_cpuid
FEATURES_PROVIDED += cpp
FEATURES_MCU_GROUP = cortex_m3_1

1
boards/frdm-k64f/Makefile.features
View File

@ -8,5 +8,6 @@ FEATURES_PROVIDED += periph_adc
FEATURES_PROVIDED += periph_rtt
FEATURES_PROVIDED += periph_rtc
FEATURES_PROVIDED += periph_random
FEATURES_PROVIDED += periph_timer
FEATURES_PROVIDED += periph_cpuid
FEATURES_MCU_GROUP = cortex_m4

1
boards/iotlab-m3/Makefile.features
View File

@ -3,6 +3,7 @@ FEATURES_PROVIDED += periph_uart
FEATURES_PROVIDED += periph_spi
FEATURES_PROVIDED += periph_i2c
FEATURES_PROVIDED += periph_rtt
FEATURES_PROVIDED += periph_timer
FEATURES_PROVIDED += periph_cpuid
FEATURES_PROVIDED += cpp
FEATURES_MCU_GROUP = cortex_m3_1

15
boards/iotlab-m3/include/board.h
View File

@ -52,13 +52,6 @@ extern "C" {
#define STDIO_RX_BUFSIZE (64U)
/** @} */
/**
* @name Assign the hardware timer
* @{
*/
#define HW_TIMER TIMER_0
/** @} */
/**
* @name Define the interface to the AT86RF231 radio
* @{
@ -151,6 +144,14 @@ extern "C" {
#define LED_ORANGE_TOGGLE (LED_ORANGE_PORT->ODR ^= (1<<LED_ORANGE_PIN))
/** @} */
/**
* @name xtimer tuning values
* @{
*/
#define XTIMER_OVERHEAD 6
#define XTIMER_SHOOT_EARLY 3
/** @} */
/**
* @brief Initialize board specific hardware, including clock, LEDs and std-IO
*/

1
boards/limifrog-v1/Makefile.features
View File

@ -2,6 +2,7 @@ FEATURES_PROVIDED += periph_gpio
FEATURES_PROVIDED += periph_uart
FEATURES_PROVIDED += periph_spi
FEATURES_PROVIDED += periph_i2c
FEATURES_PROVIDED += periph_timer
FEATURES_PROVIDED += periph_cpuid
FEATURES_PROVIDED += cpp
FEATURES_MCU_GROUP = cortex_m3_2

1
boards/mbed_lpc1768/Makefile.features
View File

@ -1,3 +1,4 @@
FEATURES_PROVIDED += cpp
FEATURES_PROVIDED += periph_uart
FEATURES_PROVIDED += periph_timer
FEATURES_MCU_GROUP = cortex_m3_1

8
boards/msb-430/include/board.h
View File

@ -44,14 +44,10 @@ extern "C" {
#define XTIMER (0)
#define XTIMER_CHAN (0)
#define XTIMER_MASK (0xffff0000)
#define XTIMER_SHIFT_ON_COMPARE (4)
#define XTIMER_BACKOFF (40)
/** @} */
/**
* @brief Defines for compatibility with hwtimer
* @deprecated
*/
#define HW_TIMER (0)
/**
* @brief Standard input/output device configuration
* @{

8
boards/msb-430h/include/board.h
View File

@ -38,14 +38,10 @@ extern "C" {
#define XTIMER (0)
#define XTIMER_CHAN (0)
#define XTIMER_MASK (0xffff0000)
#define XTIMER_SHIFT_ON_COMPARE (4)
#define XTIMER_BACKOFF (40)
/** @} */
/**
* @brief Defines for compatibility with hwtimer
* @deprecated
*/
#define HW_TIMER (0)
/**
* @brief Standard input/output device configuration
* @{

7
boards/msba2/include/board.h
View File

@ -54,9 +54,12 @@ extern "C" {
/** @} */
/**
* @brief Deprecated HW_TIMER definition (to be removed)
* @name xtimer tuning values
* @{
*/
#define HW_TIMER TIMER_DEV(0)
#define XTIMER_OVERHEAD 7
#define XTIMER_SHOOT_EARLY 3
/** @} */
/**
* @brief initialize the board's clock system

1
boards/msbiot/Makefile.features
View File

@ -7,4 +7,5 @@ FEATURES_PROVIDED += periph_pwm
FEATURES_PROVIDED += periph_random
FEATURES_PROVIDED += periph_adc
FEATURES_PROVIDED += periph_dac
FEATURES_PROVIDED += periph_timer
FEATURES_MCU_GROUP = cortex_m4

1
boards/mulle/Makefile.features
View File

@ -8,5 +8,6 @@ FEATURES_PROVIDED += periph_random
FEATURES_PROVIDED += periph_rtc
FEATURES_PROVIDED += periph_rtt
FEATURES_PROVIDED += periph_spi
FEATURES_PROVIDED += periph_timer
FEATURES_PROVIDED += periph_uart
FEATURES_MCU_GROUP = cortex_m4

6
boards/mulle/include/board.h
View File

@ -32,12 +32,6 @@
/** Disable hardware watchdog, for debugging purposes, don't use this on production builds. */
#define DISABLE_WDOG 1
/**
* @name Assign the first hardware timer.
* This timer will be used to implement an absolute reference for hwtimer_now() et al.
*/
#define HW_TIMER TIMER_0
/**
* @name Number of subsequent channels of the PIT to assign to the RIOT hardware
* timer library, starting after the HW_TIMER above.

1
boards/nrf51dongle/Makefile.features
View File

@ -5,4 +5,5 @@ FEATURES_PROVIDED += periph_gpio
FEATURES_PROVIDED += periph_random
FEATURES_PROVIDED += periph_rtt
FEATURES_PROVIDED += periph_cpuid
FEATURES_PROVIDED += periph_timer
FEATURES_MCU_GROUP = cortex_m0

1
boards/nrf6310/Makefile.features
View File

@ -6,4 +6,5 @@ FEATURES_PROVIDED += periph_random
FEATURES_PROVIDED += periph_rtt
FEATURES_PROVIDED += periph_cpuid
FEATURES_PROVIDED += periph_spi
FEATURES_PROVIDED += periph_timer
FEATURES_MCU_GROUP = cortex_m0

1
boards/nucleo-f091/Makefile.features
View File

@ -3,4 +3,5 @@ FEATURES_PROVIDED += periph_cpuid
FEATURES_PROVIDED += periph_gpio
FEATURES_PROVIDED += periph_rtc
FEATURES_PROVIDED += periph_uart
FEATURES_PROVIDED += periph_timer
FEATURES_MCU_GROUP = cortex_m0

1
boards/nucleo-f303/Makefile.features
View File

@ -5,4 +5,5 @@ FEATURES_PROVIDED += periph_pwm
FEATURES_PROVIDED += periph_uart
FEATURES_PROVIDED += periph_i2c
FEATURES_PROVIDED += periph_spi
FEATURES_PROVIDED += periph_timer
FEATURES_MCU_GROUP = cortex_m4

1
boards/nucleo-f334/Makefile.features
View File

@ -1,6 +1,7 @@
FEATURES_PROVIDED += periph_cpuid
FEATURES_PROVIDED += periph_gpio
FEATURES_PROVIDED += periph_spi
FEATURES_PROVIDED += periph_timer
FEATURES_PROVIDED += periph_uart
FEATURES_PROVIDED += cpp
FEATURES_MCU_GROUP = cortex_m4

8
boards/nucleo-f334/include/board.h
View File

@ -74,6 +74,14 @@ extern "C" {
#define LED_ORANGE_TOGGLE
/** @} */
/**
* @name xtimer tuning values
* @{
*/
#define XTIMER_OVERHEAD 5
#define XTIMER_SHOOT_EARLY 2
/** @} */
/**
* @brief Initialize board specific hardware, including clock, LEDs and std-IO
*/

9
boards/nucleo-f334/include/periph_conf.h
View File

@ -108,15 +108,6 @@ extern "C" {
#define SPI_0_MOSI_PORT_CLKEN() (RCC->AHBENR |= RCC_AHBENR_GPIOAEN)
/** @} */
/**
* @name xtimer configuration
* @{
*/
#define XTIMER_USLEEP_UNTIL_OVERHEAD 10
#define XTIMER_BACKOFF 15
#define XTIMER_OVERHEAD 3
/** @} */
#ifdef __cplusplus
}
#endif

1
boards/nucleo-l1/Makefile.features
View File

@ -3,5 +3,6 @@ FEATURES_PROVIDED += periph_uart
FEATURES_PROVIDED += periph_spi
FEATURES_PROVIDED += periph_i2c
FEATURES_PROVIDED += periph_cpuid
FEATURES_PROVIDED += periph_timer
FEATURES_PROVIDED += cpp
FEATURES_MCU_GROUP = cortex_m3_2

1
boards/openmote/Makefile.features
View File

@ -3,4 +3,5 @@ FEATURES_PROVIDED += periph_uart
FEATURES_PROVIDED += periph_gpio
FEATURES_PROVIDED += periph_random
FEATURES_PROVIDED += periph_cpuid
FEATURES_PROVIDED += periph_timer
FEATURES_MCU_GROUP = cortex_m3_2

1
boards/pba-d-01-kw2x/Makefile.features
View File

@ -7,5 +7,6 @@ FEATURES_PROVIDED += periph_adc
FEATURES_PROVIDED += periph_rtt
FEATURES_PROVIDED += periph_rtc
FEATURES_PROVIDED += periph_random
FEATURES_PROVIDED += periph_timer
FEATURES_PROVIDED += periph_cpuid
FEATURES_MCU_GROUP = cortex_m4

1
boards/pca10000/Makefile.features
View File

@ -5,4 +5,5 @@ FEATURES_PROVIDED += periph_gpio
FEATURES_PROVIDED += periph_random
FEATURES_PROVIDED += periph_rtt
FEATURES_PROVIDED += periph_cpuid
FEATURES_PROVIDED += periph_timer
FEATURES_MCU_GROUP = cortex_m0

10
boards/pca10000/include/board.h
View File

@ -34,9 +34,15 @@ extern "C" {
#define F_CPU (16000000UL)
/**
* @brief Assign the hardware timer
* @brief Xtimer configuration
* @{
*/
#define HW_TIMER TIMER_0
#define XTIMER (0)
#define XTIMER_CHAN (0)
#define XTIMER_MASK (0xff000000)
#define XTIMER_SHIFT_ON_COMPARE (2)
#define XTIMER_BACKOFF (40)
/** @} */
/**
* @name Define the boards stdio

1
boards/pca10005/Makefile.features
View File

@ -6,4 +6,5 @@ FEATURES_PROVIDED += periph_random
FEATURES_PROVIDED += periph_rtt
FEATURES_PROVIDED += periph_cpuid
FEATURES_PROVIDED += periph_spi
FEATURES_PROVIDED += periph_timer
FEATURES_MCU_GROUP = cortex_m0

16
boards/pca10005/include/board.h
View File

@ -33,6 +33,17 @@ extern "C" {
*/
#define F_CPU (16000000UL)
/**
* @brief Xtimer configuration
* @{
*/
#define XTIMER (0)
#define XTIMER_CHAN (0)
#define XTIMER_MASK (0xff000000)
#define XTIMER_SHIFT_ON_COMPARE (2)
#define XTIMER_BACKOFF (40)
/** @} */
/**
* @name Define the boards stdio
* @{
@ -42,11 +53,6 @@ extern "C" {
#define STDIO_RX_BUFSIZE (64U)
/** @} */
/**
* @name Assign the hardware timer
*/
#define HW_TIMER TIMER_0
/**
* @name Macros for controlling the on-board LEDs.
* @{

1
boards/remote/Makefile.features
View File

@ -3,4 +3,5 @@ FEATURES_PROVIDED += periph_uart
FEATURES_PROVIDED += periph_gpio
FEATURES_PROVIDED += periph_random
FEATURES_PROVIDED += periph_cpuid
FEATURES_PROVIDED += periph_timer
FEATURES_MCU_GROUP = cortex_m3_2

3
boards/samr21-xpro/include/board.h
View File

@ -38,7 +38,8 @@ extern "C" {
/**
* Assign the hardware timer
*/
#define HW_TIMER TIMER_1
#define XTIMER TIMER_1
#define XTIMER_CHAN (0)
/**
* @name AT86RF233 configuration

1
boards/spark-core/Makefile.features
View File

@ -1,4 +1,5 @@
FEATURES_PROVIDED += cpp
FEATURES_PROVIDED += periph_uart
FEATURES_PROVIDED += periph_gpio
FEATURES_PROVIDED += periph_timer
FEATURES_MCU_GROUP = cortex_m3_2

1
boards/stm32f0discovery/Makefile.features
View File

@ -4,4 +4,5 @@ FEATURES_PROVIDED += periph_spi
FEATURES_PROVIDED += periph_uart
FEATURES_PROVIDED += cpp
FEATURES_PROVIDED += periph_cpuid
FEATURES_PROVIDED += periph_timer
FEATURES_MCU_GROUP = cortex_m0

1
boards/stm32f3discovery/Makefile.features
View File

@ -5,4 +5,5 @@ FEATURES_PROVIDED += periph_pwm
FEATURES_PROVIDED += periph_i2c
FEATURES_PROVIDED += periph_spi
FEATURES_PROVIDED += periph_cpuid
FEATURES_PROVIDED += periph_timer
FEATURES_MCU_GROUP = cortex_m4

1
boards/stm32f4discovery/Makefile.features
View File

@ -8,6 +8,7 @@ FEATURES_PROVIDED += periph_random
FEATURES_PROVIDED += periph_adc
FEATURES_PROVIDED += periph_dac
FEATURES_PROVIDED += periph_cpuid
FEATURES_PROVIDED += periph_timer
FEATURES_MCU_GROUP = cortex_m4
FEATURES_CONFLICT += periph_spi:periph_dac

9
boards/stm32f4discovery/include/board.h
View File

@ -34,9 +34,14 @@ extern "C" {
#define F_CPU CLOCK_CORECLOCK
/**
* @name Assign the hardware timer
* @name xtimer configuration
* @{
*/
#define HW_TIMER TIMER_0
#define XTIMER TIMER_0
#define XTIMER_CHAN (0)
#define XTIMER_OVERHEAD (6)
#define XTIMER_BACKOFF (5)
/** @} */
/**
* @name Define UART device and baudrate for stdio

8
boards/telosb/include/board.h
View File

@ -44,14 +44,10 @@ extern "C" {
#define XTIMER (0)
#define XTIMER_CHAN (0)
#define XTIMER_MASK (0xffff0000)
#define XTIMER_SHIFT_ON_COMPARE (4)
#define XTIMER_BACKOFF (40)
/** @} */
/**
* @brief Defines for compatibility with hwtimer
* @deprecated
*/
#define HW_TIMER (0)
/**
* @brief Standard input/output device configuration
* @{

1
boards/udoo/Makefile.features
View File

@ -3,4 +3,5 @@ FEATURES_PROVIDED += periph_uart
FEATURES_PROVIDED += periph_gpio
FEATURES_PROVIDED += periph_spi
FEATURES_PROVIDED += periph_random
FEATURES_PROVIDED += periph_timer
FEATURES_MCU_GROUP = cortex_m3_2

8
boards/wsn430-v1_3b/include/board.h
View File

@ -46,14 +46,10 @@ extern "C" {
#define XTIMER (0)
#define XTIMER_CHAN (0)
#define XTIMER_MASK (0xffff0000)
#define XTIMER_SHIFT_ON_COMPARE (4)
#define XTIMER_BACKOFF (40)
/** @} */
/**
* @brief Defines for compatibility with hwtimer
* @deprecated
*/
#define HW_TIMER (0)
/**
* @brief Standard input/output device configuration
* @{

8
boards/wsn430-v1_4/include/board.h
View File

@ -46,14 +46,10 @@ extern "C" {
#define XTIMER (0)
#define XTIMER_CHAN (0)
#define XTIMER_MASK (0xffff0000)
#define XTIMER_SHIFT_ON_COMPARE (4)
#define XTIMER_BACKOFF (40)
/** @} */
/**
* @brief Defines for compatibility with hwtimer
* @deprecated
*/
#define HW_TIMER (0)
/**
* @brief Standard input/output device configuration
* @{

1
boards/yunjia-nrf51822/Makefile.features
View File

@ -6,4 +6,5 @@ FEATURES_PROVIDED += periph_random
FEATURES_PROVIDED += periph_rtt
FEATURES_PROVIDED += periph_cpuid
FEATURES_PROVIDED += periph_spi
FEATURES_PROVIDED += periph_timer
FEATURES_MCU_GROUP = cortex_m0

16
boards/yunjia-nrf51822/include/board.h
View File

@ -32,6 +32,17 @@ extern "C" {
*/
#define F_CPU (16000000UL)
/**
* @brief Xtimer configuration
* @{
*/
#define XTIMER (0)
#define XTIMER_CHAN (0)
#define XTIMER_MASK (0xff000000)
#define XTIMER_SHIFT_ON_COMPARE (2)
#define XTIMER_BACKOFF (40)
/** @} */
/**
* @name Define the boards stdio
* @{
@ -41,11 +52,6 @@ extern "C" {
#define STDIO_RX_BUFSIZE (64U)
/** @} */
/**
* @name Assign the hardware timer
*/
#define HW_TIMER TIMER_0
/**
* @name Macros for controlling the on-board LEDs.
* @{

8
boards/z1/include/board.h
View File

@ -46,14 +46,10 @@ extern "C" {
#define XTIMER (0)
#define XTIMER_CHAN (0)
#define XTIMER_MASK (0xffff0000)
#define XTIMER_SHIFT_ON_COMPARE (4)
#define XTIMER_BACKOFF (40)
/** @} */
/**
* @brief Defines for compatibility with hwtimer
* @deprecated
*/
#define HW_TIMER (0)
/**
* @brief Standard input/output device configuration
* @{

213
core/hwtimer.c
View File

@ -1,213 +0,0 @@
/*
* Copyright (C) 2014 Freie Universität Berlin
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @ingroup core_hwtimer
* @{
*
* @file
* @brief Hardware timer abstraction implementation
*
* @author Heiko Will <hwill@inf.fu-berlin.de>
* @author Thomas Hillebrandt <hillebra@inf.fu-berlin.de>
* @author Kaspar Schleiser <kaspar@schleiser.de>
* @author Oliver Hahm <oliver.hahm@fu-berlin.de>
* @author Kévin Roussel <Kevin.Roussel@inria.fr>
*
* @}
*/
#include <stdio.h>
#include "kernel.h"
#include "thread.h"
#include "lifo.h"
#include "mutex.h"
#include "irq.h"
#include "board.h"
#define ENABLE_DEBUG (0)
#include "debug.h"
#include "log.h"
#include "hwtimer.h"
#include "hwtimer_cpu.h"
#include "arch/hwtimer_arch.h"
/*---------------------------------------------------------------------------*/
typedef struct hwtimer_t {
void (*callback)(void*);
void *data;
} hwtimer_t;
static hwtimer_t timer[HWTIMER_MAXTIMERS];
static int lifo[HWTIMER_MAXTIMERS + 1];
/*---------------------------------------------------------------------------*/
static void multiplexer(int source)
{
lifo_insert(lifo, source);
lpm_prevent_sleep--;
timer[source].callback(timer[source].data);
}
static void hwtimer_releasemutex(void* mutex) {
mutex_unlock((mutex_t*) mutex);
}
void hwtimer_spin(unsigned long ticks)
{
DEBUG("hwtimer_spin ticks=%lu\n", ticks);
unsigned long start = hwtimer_arch_now();
/* compute destination time, possibly resulting in an overflow */
unsigned long stop = ((start + ticks) & HWTIMER_MAXTICKS);
/*
* If there is an overflow (that is: stop time is inferior to start),
* hwtimer_arch_now needs to spin until it has overflowed as well.
*/
if (stop < start) {
while (hwtimer_arch_now() > start) /* do nothing */;
}
/* wait until we have passed destination (stop) time */
while (hwtimer_arch_now() < stop) /* do nothing again */;
}
/*---------------------------------------------------------------------------*/
void hwtimer_init(void)
{
hwtimer_init_comp(F_CPU);
}
/*---------------------------------------------------------------------------*/
void hwtimer_init_comp(uint32_t fcpu)
{
hwtimer_arch_init(multiplexer, fcpu);
lifo_init(lifo, HWTIMER_MAXTIMERS);
for (int i = 0; i < HWTIMER_MAXTIMERS; i++) {
lifo_insert(lifo, i);
}
}
/*---------------------------------------------------------------------------*/
int hwtimer_active(void)
{
return (!lifo_empty(lifo));
}
/*---------------------------------------------------------------------------*/
unsigned long hwtimer_now(void)
{
return hwtimer_arch_now();
}
/*---------------------------------------------------------------------------*/
void hwtimer_wait(unsigned long ticks)
{
DEBUG("hwtimer_wait ticks=%lu\n", ticks);
if ((ticks <= (HWTIMER_SPIN_BARRIER)) || inISR()) {
hwtimer_spin(ticks);
return;
}
mutex_t mutex = MUTEX_INIT;
mutex_lock(&mutex);
int res = hwtimer_set(ticks - (HWTIMER_WAIT_OVERHEAD), hwtimer_releasemutex, &mutex);
if (res == -1) {
mutex_unlock(&mutex);
hwtimer_spin(ticks);
return;
}
/* try to lock mutex again will cause the thread to go into
* STATUS_MUTEX_BLOCKED until hwtimer fires the releasemutex */
mutex_lock(&mutex);
}
/*---------------------------------------------------------------------------*/
static int _hwtimer_set(unsigned long offset, void (*callback)(void*), void *ptr, bool absolute)
{
DEBUG("_hwtimer_set: offset=%lu callback=%p ptr=%p absolute=%d\n", offset, callback, ptr, absolute);
unsigned state;
state = disableIRQ();
int n = lifo_get(lifo);
if (n == -1) {
restoreIRQ(state);
LOG_WARNING("No hwtimer left.\n");
return -1;
}
timer[n].callback = callback;
timer[n].data = ptr;
if (absolute) {
DEBUG("hwtimer_arch_set_absolute n=%d\n", n);
hwtimer_arch_set_absolute(offset, n);
}
else {
DEBUG("hwtimer_arch_set n=%d\n", n);
hwtimer_arch_set(offset, n);
}
lpm_prevent_sleep++;
restoreIRQ(state);
return n;
}
int hwtimer_set(unsigned long offset, void (*callback)(void*), void *ptr)
{
return _hwtimer_set(offset, callback, ptr, false);
}
int hwtimer_set_absolute(unsigned long offset, void (*callback)(void*), void *ptr)
{
return _hwtimer_set(offset, callback, ptr, true);
}
/*---------------------------------------------------------------------------*/
int hwtimer_remove(int n)
{
DEBUG("hwtimer_remove n=%d\n", n);
unsigned state = disableIRQ();
hwtimer_arch_unset(n);
lifo_insert(lifo, n);
timer[n].callback = NULL;
lpm_prevent_sleep--;
restoreIRQ(state);
return 1;
}

85
core/include/arch/hwtimer_arch.h
View File

@ -1,85 +0,0 @@
/*
* Copyright (C) 2014 Freie Universität Berlin
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @ingroup core_arch
* @{
*
* @file
* @brief The kernel's hardware timer abstraction interface
*
* @author Thomas Hillebrandt <hillebra@inf.fu-berlin.de>
* @author Heiko Will <hwill@inf.fu-berlin.de>
* @author Kaspar Schleiser <kaspar@schleiser.de>
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
*/
#ifndef HWTIMER_ARCH_H_
#define HWTIMER_ARCH_H_
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
/**
* @brief Initialize architecture dependent kernel timer support
*
* @param[in] handler callback that is called when timer @p offset is reached
* @param[in] fcpu the core CPU-frequency for tick interval calculation
*/
void hwtimer_arch_init(void (*handler)(int), uint32_t fcpu);
/**
* @brief Enable interrupts of hardware timers
*/
void hwtimer_arch_enable_interrupt(void);
/**
* @brief Disable interrupts of hardware timers
*/
void hwtimer_arch_disable_interrupt(void);
/**
* @brief Set a kernel timer to raise an interrupt after @p offset kernel timer
* ticks from now
*
* @param[in] offset number of ticks until the timer fires
* @param[in] timer the channel to set
*/
void hwtimer_arch_set(unsigned long offset, short timer);
/**
* @brief Set a kernel timer to raise an interrupt at specified system time.
*
* @param[in] value absolute timer tick value to set a timer channel to
* @param[in] timer the channel to set
*/
void hwtimer_arch_set_absolute(unsigned long value, short timer);
/**
* @brief Unset the kernel timer with the given timer ID
*
* @param[in] timer the channel to unset
*/
void hwtimer_arch_unset(short timer);
/**
* @brief Get the current tick count of the default hardware timer
*
* @return the current value of the hwtimer
*/
unsigned long hwtimer_arch_now(void);
#ifdef __cplusplus
}
#endif
#endif /* HWTIMER_ARCH_H_ */
/** @} */

196
core/include/hwtimer.h
View File

@ -1,196 +0,0 @@
/*
* Copyright (C) 2013 Freie Universität Berlin
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @defgroup core_hwtimer Hardware timer
* @ingroup core
* @brief Hardware timer interface
*
* The Hardware timers are directly mapped to hardware timers with minimum
* latency. They are intended for short intervals and to be used in time
* critical low-level drivers (e.g. radio). hwtimer callbacks are run in the
* interrupt context and must use the shortest possible execution time (e.g.
* set a flag and trigger a worker thread).
*
* <b>The hardware timer should not be used (until you know what
* you're doing)</b>, use \ref sys_vtimer instead.
*
* @{
*
* @file
* @brief HW-timer abstraction
*
* @author Heiko Will
* @author Kaspar Schleiser <kaspar@schleiser.de>
* @author Michael Baar
*/
#ifndef HWTIMER_H
#define HWTIMER_H
#include <stdint.h>
#include "hwtimer_cpu.h"
#include "board.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief Number of kernel timer ticks per second
* @def HWTIMER_SPEED
*/
#ifndef HWTIMER_SPEED
#warning "HWTIMER_SPEED undefined. Set HWTIMER_SPEED to the number of ticks \
per second for the current architecture."
#endif
/**
* @brief Upper bound for hwtimer_spin
*
* @note Barrier starting from which hwtimer_spin is called instead
* of setting a timer and yielding the thread.
*
* Boards should override this.
*
* @def HWTIMER_SPIN_BARRIER
*/
#ifndef HWTIMER_SPIN_BARRIER
#define HWTIMER_SPIN_BARRIER (6)
#endif
/**
* @brief Overhead of the `hwtimer_wait` function
*
* @note This value is used to decrease the number of ticks that
* `hwtimer_wait` uses to set the actual hardware timer.
*
* The goal is to make sure the number of ticks spent in the
* function corresponds to the ticks argument it was given.
*
* Boards should override this.
*
* @def HWTIMER_WAIT_OVERHEAD
*/
#ifndef HWTIMER_WAIT_OVERHEAD
#define HWTIMER_WAIT_OVERHEAD (2)
#endif
/**
* @brief Convert microseconds to kernel timer ticks
* @param[in] us number of microseconds
* @return kernel timer ticks
*/
#if HWTIMER_SPEED > 1000000L
#define HWTIMER_TICKS(us) ((us) * (HWTIMER_SPEED / 1000000L))
#else
#define HWTIMER_TICKS(us) ((us) / (1000000L / HWTIMER_SPEED))
#endif
/**
* @brief Convert ticks to microseconds
* @param[in] ticks number of ticks
* @return microseconds
*/
#if HWTIMER_SPEED > 1000000L
#define HWTIMER_TICKS_TO_US(ticks) ((ticks) / (HWTIMER_SPEED / 1000000L))
#else
#define HWTIMER_TICKS_TO_US(ticks) ((ticks) * (1000000L / HWTIMER_SPEED))
#endif
/**
* @brief Maximum hwtimer tick count (before overflow)
* @def HWTIMER_MAXTICKS
*/
#ifndef HWTIMER_MAXTICKS
#warning "HWTIMER_MAXTICKS undefined. Set HWTIMER_MAXTICKS to the maximum \
number of ticks countable on the current architecture."
#endif
/**
* @brief microseconds before hwtimer overflow
*/
#if HWTIMER_SPEED > 1000000L
#define HWTIMER_OVERFLOW_MICROS() (HWTIMER_MAXTICKS / HWTIMER_SPEED * 1000000L)
#else
#define HWTIMER_OVERFLOW_MICROS() (1000000L / HWTIMER_SPEED * HWTIMER_MAXTICKS)
#endif
typedef uint32_t timer_tick_t; /**< data type for hwtimer ticks */
/**
* @brief initialize the hwtimer module
*/
void hwtimer_init(void);
/**
* @brief Get the hardware time
* @return The current tick count of the hardware timer
*/
unsigned long hwtimer_now(void);
/**
* @brief Set a kernel timer
* @param[in] offset Offset until callback invocation in timer ticks
* @param[in] callback Callback function
* @param[in] ptr Argument to callback function
* @return timer id
*/
int hwtimer_set(unsigned long offset, void (*callback)(void*), void *ptr);
/**
* @brief Set a kernel timer
* @param[in] absolute Absolute timer counter value for invocation
* of handler
* @param[in] callback Callback function
* @param[in] ptr Argument to callback function
* @return timer id
*/
int hwtimer_set_absolute(unsigned long absolute,
void (*callback)(void*), void *ptr);
/**
* @brief Remove a kernel timer
* @param[in] t Id of timer to remove
* @return 1 on success
*/
int hwtimer_remove(int t);
/**
* @brief Delay current thread
* @param[in] ticks Number of kernel ticks to delay
*/
void hwtimer_wait(unsigned long ticks);
/**
* @brief determine if the hwtimer module is initialized
* @return 1 if the hwtimer module is initialized
*/
int hwtimer_active(void);
/**
* @brief initialize hwtimer module data structures and hardware
*
* @param[in] fcpu cpu frequency
*/
void hwtimer_init_comp(uint32_t fcpu);
/**
* @brief Delay current thread, spinning. Use only in interrupts for
* VERY short delays!
*
* @param[in] ticks Number of kernel ticks to delay
*/
void hwtimer_spin(unsigned long ticks);
#ifdef __cplusplus
}
#endif
/** @} */
#endif /* HWTIMER_H */

2
core/include/sched.h
View File

@ -164,7 +164,7 @@ extern volatile kernel_pid_t sched_active_pid;
*/
extern clist_node_t *sched_runqueues[SCHED_PRIO_LEVELS];
#if SCHEDSTATISTICS
#ifdef MODULE_SCHEDSTATISTICS
/**
* Scheduler statistics
*/

12
core/kernel_init.c
View File

@ -29,10 +29,13 @@
#include "cpu.h"
#include "lpm.h"
#include "thread.h"
#include "hwtimer.h"
#include "irq.h"
#include "log.h"
#ifdef MODULE_SCHEDSTATISTICS
#include "sched.h"
#endif
#define ENABLE_DEBUG (0)
#include "debug.h"
@ -51,6 +54,11 @@ static void *main_trampoline(void *arg)
auto_init();
#endif
#ifdef MODULE_SCHEDSTATISTICS
schedstat *stat = &sched_pidlist[thread_getpid()];
stat->laststart = 0;
#endif
LOG_INFO("main(): This is RIOT! (Version: " RIOT_VERSION ")\n");
main();
@ -85,8 +93,6 @@ void kernel_init(void)
{
(void) disableIRQ();
hwtimer_init();
thread_create(idle_stack, sizeof(idle_stack),
THREAD_PRIORITY_IDLE,
CREATE_WOUT_YIELD | CREATE_STACKTEST,

16
core/sched.c
View File

@ -31,8 +31,8 @@
#include "irq.h"
#include "log.h"
#if SCHEDSTATISTICS
#include "hwtimer.h"
#ifdef MODULE_SCHEDSTATISTICS
#include "xtimer.h"
#endif
#define ENABLE_DEBUG (0)
@ -55,7 +55,7 @@ volatile kernel_pid_t sched_active_pid = KERNEL_PID_UNDEF;
clist_node_t *sched_runqueues[SCHED_PRIO_LEVELS];
static uint32_t runqueue_bitcache = 0;
#if SCHEDSTATISTICS
#ifdef MODULE_SCHEDSTATISTICS
static void (*sched_cb) (uint32_t timestamp, uint32_t value) = NULL;
schedstat sched_pidlist[KERNEL_PID_LAST + 1];
#endif
@ -81,8 +81,8 @@ int sched_run(void)
return 0;
}
#ifdef SCHEDSTATISTICS
unsigned long time = hwtimer_now();
#ifdef MODULE_SCHEDSTATISTICS
unsigned long time = xtimer_now();
#endif
if (active_thread) {
@ -96,7 +96,7 @@ int sched_run(void)
}
#endif
#ifdef SCHEDSTATISTICS
#ifdef MODULE_SCHEDSTATISTICS
schedstat *active_stat = &sched_pidlist[active_thread->pid];
if (active_stat->laststart) {
active_stat->runtime_ticks += time - active_stat->laststart;
@ -104,7 +104,7 @@ int sched_run(void)
#endif
}
#if SCHEDSTATISTICS
#ifdef MODULE_SCHEDSTATISTICS
schedstat *next_stat = &sched_pidlist[next_thread->pid];
next_stat->laststart = time;
next_stat->schedules++;
@ -122,7 +122,7 @@ int sched_run(void)
return 1;
}
#if SCHEDSTATISTICS
#ifdef MODULE_SCHEDSTATISTICS
void sched_register_cb(void (*callback)(uint32_t, uint32_t))
{
sched_cb = callback;

1
core/thread.c
View File

@ -29,7 +29,6 @@
#include "debug.h"
#include "kernel_internal.h"
#include "bitarithm.h"
#include "hwtimer.h"
#include "sched.h"
volatile tcb_t *thread_get(kernel_pid_t pid)

37
cpu/arm7_common/include/hwtimer_cpu.h
View File

@ -1,37 +0,0 @@
/*
* Copyright (C) 2009 Freie Universität Berlin
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/*
* lpc2387_timer_0_1.h
*
* Created on: 15.01.2009
* Author: heiko, kaspar
*
* Changelog:
* 26.01.09 kaspar: renamed file, misc changes for firekernel
*/
#ifndef HWTIMER_CPU_H_
#define HWTIMER_CPU_H_
#ifdef __cplusplus
extern "C" {
#endif
#define HWTIMER_MAXTIMERS 4
#define HWTIMER_SPEED 1000000
#define HWTIMER_MAXTICKS (0xFFFFFFFF)
#define HWTIMER_MSEC (HWTIMER_SPEED/1000)
#define HWTIMER_SEC (HWTIMER_SPEED)
#ifdef __cplusplus
}
#endif
#endif /* HWTIMER_CPU_H_ */

3
cpu/atmega2560/Makefile.include
View File

@ -4,9 +4,6 @@ export CFLAGS += -DCOREIF_NG=1
# tell the build system that the CPU depends on the atmega common files
USEMODULE += atmega_common
# use hwtimer compatibility module
USEMODULE += hwtimer_compat
# export the peripheral drivers to be linked into the final binary
export USEMODULE += periph

40
cpu/atmega2560/include/hwtimer_cpu.h
View File

@ -1,40 +0,0 @@
/*
* Copyright (C) 2014 Freie Universität Berlin, Hinnerk van Bruinehsen
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @ingroup cpu_atmega2560
* @{
*
* @file
* @brief CPU specific hwtimer configuration options
*
* @author Hinnerk van Bruinehsen <h.v.bruinehsen@fu-berlin.de>
*/
#ifndef __HWTIMER_CPU_H
#define __HWTIMER_CPU_H
#ifdef __cplusplus
extern "C" {
#endif
/**
* @name Hardware timer configuration
* @{
*/
#define HWTIMER_MAXTIMERS 3 /**< the CPU implementation supports 3 HW timers */
#define HWTIMER_SPEED 1000000 /**< the HW timer runs with 1MHz */
#define HWTIMER_MAXTICKS (0xFFFF) /**< 16-bit timer */
/** @} */
#ifdef __cplusplus
}
#endif
#endif /* __HWTIMER_CPU_H */
/** @} */

22
cpu/atmega2560/periph/timer.c
View File

@ -278,7 +278,8 @@ int timer_clear(tim_t dev, int channel)
unsigned int timer_read(tim_t dev)
{
uint16_t value;
uint16_t a;
uint32_t b;
/*
* Disabling interrupts globally because read from 16 Bit register can
* otherwise be messed up
@ -289,29 +290,38 @@ unsigned int timer_read(tim_t dev)
#if TIMER_0_EN
case TIMER_0:
value = TIMER0_COUNTER;
do {
a = TIMER0_COUNTER;
b = TIMER0_COUNTER;
} while (a != b);
break;
#endif
#if TIMER_1_EN
case TIMER_1:
value = TIMER1_COUNTER;
do {
a = TIMER1_COUNTER;
b = TIMER1_COUNTER;
} while (a != b);
break;
#endif
#if TIMER_2_EN
case TIMER_2:
value = TIMER2_COUNTER;
do {
a = TIMER2_COUNTER;
b = TIMER2_COUNTER;
} while (a != b);
break;
#endif
case TIMER_UNDEFINED:
default:
value = 0;
a = 0;
}
restoreIRQ(state);
return value;
return a;
}
void timer_stop(tim_t dev)

72
cpu/cc2538/hwtimer_arch.c
View File

@ -1,72 +0,0 @@
/*
* Copyright (C) 2014 Freie Universität Berlin
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @ingroup cpu_cc2538
* @{
*
* @file
* @brief Implementation of the kernels hwtimer interface
*
* The hardware timer implementation uses the Cortex build-in system timer as back-end.
*
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
*
* @}
*/
#include "arch/hwtimer_arch.h"
#include "board.h"
#include "periph/timer.h"
#include "hwtimer_cpu.h"
void irq_handler(int channel);
void (*timeout_handler)(int);
void hwtimer_arch_init(void (*handler)(int), uint32_t fcpu)
{
timeout_handler = handler;
timer_init(HW_TIMER, HWTIMER_SPEED / 1000000, &irq_handler);
}
void hwtimer_arch_enable_interrupt(void)
{
timer_irq_enable(HW_TIMER);
}
void hwtimer_arch_disable_interrupt(void)
{
timer_irq_disable(HW_TIMER);
}
void hwtimer_arch_set(unsigned long offset, short timer)
{
timer_set(HW_TIMER, timer, offset);
}
void hwtimer_arch_set_absolute(unsigned long value, short timer)
{
timer_set_absolute(HW_TIMER, timer, value);
}
void hwtimer_arch_unset(short timer)
{
timer_clear(HW_TIMER, timer);
}
unsigned long hwtimer_arch_now(void)
{
return timer_read(HW_TIMER);
}
void irq_handler(int channel)
{
timeout_handler((short)(channel));
}

40
cpu/cc2538/include/hwtimer_cpu.h
View File

@ -1,40 +0,0 @@
/*
* Copyright (C) 2014 Loci Controls Inc.
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @ingroup cpu_cc2538
* @{
*
* @file
* @brief CPU specific hwtimer configuration options
*
* @author Ian Martin <ian@locicontrols.com>
*/
#ifndef __HWTIMER_CPU_H
#define __HWTIMER_CPU_H
#ifdef __cplusplus
extern "C" {
#endif
/**
* @name Hardware timer configuration
* @{
*/
#define HWTIMER_MAXTIMERS 2 /**< Number of hwtimers */
#define HWTIMER_SPEED 1000000 /**< The hardware timer runs at 1MHz */
#define HWTIMER_MAXTICKS 0xFFFFFFFF /**< 32-bit timer */
/** @} */
#ifdef __cplusplus
} /* end extern "C" */
#endif
#endif /* __HWTIMER_CPU_H */
/** @} */

2
cpu/cc430/Makefile.include
View File

@ -2,4 +2,4 @@ INCLUDES += -I$(RIOTBASE)/cpu/cc430/include/
include $(RIOTCPU)/msp430-common/Makefile.include
export USEMODULE += periph hwtimer_compat
export USEMODULE += periph

8
cpu/cc430/cc430-adc.c
View File

@ -51,7 +51,7 @@
#include "irq.h"
#include "cpu.h"
#include "cc430-adc.h"
#include "hwtimer.h"
#include "xtimer.h"
uint16_t adc12_result;
uint8_t adc12_data_ready;
@ -74,8 +74,8 @@ uint16_t adc12_single_conversion(uint16_t ref, uint16_t sht, uint16_t channel)
ADC12IE = 0x001; /* ADC_IFG upon conv result-ADCMEMO */
enableIRQ();
/* Wait 2 ticks (66us) to allow internal reference to settle */
hwtimer_wait(2);
/* Wait 66us to allow internal reference to settle */
xtimer_usleep(66);
/* Start ADC12 */
ADC12CTL0 |= ADC12ENC;
@ -87,7 +87,7 @@ uint16_t adc12_single_conversion(uint16_t ref, uint16_t sht, uint16_t channel)
ADC12CTL0 |= ADC12SC;
/* Wait until ADC12 has finished */
hwtimer_wait(5);
xtimer_usleep(150);
while (!adc12_data_ready);

10
cpu/cc430/cc430-gpioint.c
View File

@ -20,7 +20,7 @@
#include "bitarithm.h"
#include "cpu.h"
#include "irq.h"
#include "hwtimer.h"
#include "xtimer.h"
/** min and max portnumber to generate interrupts */
#define PORTINT_MIN (1)
@ -163,10 +163,10 @@ interrupt(PORT1_VECTOR) __attribute__((naked)) port1_isr(void)
/* check interrupt source */
if (debounce_flags[0] & p1ifg) {
/* check if bouncing */
diff = hwtimer_now() - debounce_time[0][ifg_num];
diff = xtimer_now() - debounce_time[0][ifg_num];
if (diff > DEBOUNCE_TIMEOUT) {
debounce_time[0][ifg_num] = hwtimer_now();
debounce_time[0][ifg_num] = xtimer_now();
if (cb[0][ifg_num] != NULL) {
cb[0][ifg_num]();
@ -208,10 +208,10 @@ interrupt(PORT2_VECTOR) __attribute__((naked)) port2_isr(void)
/* check interrupt source */
if (debounce_flags[1] & p2ifg) {
/* check if bouncing */
diff = hwtimer_now() - debounce_time[1][ifg_num];
diff = xtimer_now() - debounce_time[1][ifg_num];
if (diff > DEBOUNCE_TIMEOUT) {
debounce_time[1][ifg_num] = hwtimer_now();
debounce_time[1][ifg_num] = xtimer_now();
c1++;
if (cb[1][ifg_num] != NULL) {

8
cpu/cortexm_common/reboot_arch.c
View File

@ -1,5 +1,6 @@
/*
* Copyright (C) 2014-2015 Freie Universität Berlin
* 2015 Kaspar Schleiser <kaspar@schleiser.de>
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
@ -14,6 +15,7 @@
* @brief Implementation of the kernels reboot interface
*
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
* @author Kaspar Schleiser <kaspar@schleiser.de>
*
* @}
*/
@ -22,13 +24,13 @@
#include "arch/reboot_arch.h"
#include "cpu.h"
#include "hwtimer.h"
int reboot_arch(int mode)
{
printf("Going into reboot, mode %i\n", mode);
/* wait 1 ms to make sure the printf is finished */
hwtimer_wait(HWTIMER_TICKS(1000));
/* wait a while to make sure the printf is finished */
volatile int n = 100000;
while(n--);
NVIC_SystemReset();
return -1;
}

43
cpu/k60/include/hwtimer_cpu.h
View File

@ -1,43 +0,0 @@
/*
* Copyright (C) 2015 Eistec AB
*
* This file is subject to the terms and conditions of the GNU Lesser General
* Public License v2.1. See the file LICENSE in the top level directory for more
* details.
*/
/**
* @ingroup cpu_k60
* @{
*
* @file
* @brief CPU specific hwtimer configuration options
*
* @author Hauke Petersen <hauke.peterse@fu-berlin.de>
*/
#ifndef HWTIMER_CPU_H_
#define HWTIMER_CPU_H_
#include "cpu.h"
#ifdef __cplusplus
extern "C"
{
#endif
/**
* @name Hardware timer configuration
* @{
*/
#define HWTIMER_MAXTIMERS 1 /**< the HW timer is using the LPTMR as its hardware timer */
#define HWTIMER_SPEED 32768 /**< LPTMR is running at 32.768 kHz */
#define HWTIMER_MAXTICKS (0xFFFFFFFF) /**< Virtually extended to 32 bits from 16 bits hardware counter. */
/** @} */
#ifdef __cplusplus
}
#endif
#endif /* HWTIMER_CPU_H_ */
/** @} */

357
cpu/kinetis_common/hwtimer_arch.c
View File

@ -1,357 +0,0 @@
/*
* Copyright (C) 2014 PHYTEC Messtechnik GmbH
* Copyright (C) 2015 Eistec AB
*
* This file is subject to the terms and conditions of the GNU Lesser General
* Public License v2.1. See the file LICENSE in the top level directory for more
* details.
*/
/**
* @ingroup cpu_kinetis_common_hwtimer
* @{
*
* @file
* @brief Implementation of the kernel hwtimer interface.
* hwtimer uses Freescale Low Power Timer LPTMR0.
*
* @author Johann Fischer <j.fischer@phytec.de>
* @author Joakim Gebart <joakim.gebart@eistec.se>
*
* @}
*/
#include "arch/hwtimer_arch.h"
#include "hwtimer_cpu.h"
#include "cpu_conf.h"
#include "thread.h"
#define ENABLE_DEBUG (0)
#include "debug.h"
#define ENABLE_STATS (0)
#if ENABLE_STATS
/* Collect some statistics */
struct {
unsigned int count_set_total;
unsigned int count_set_absolute;
unsigned int count_unset_total;
unsigned int count_isr_total;
unsigned int count_isr_rollover;
unsigned int count_isr_handler_call;
unsigned int count_isr_unset;
} hwtimer_stats = {
.count_set_total = 0,
.count_set_absolute = 0,
.count_unset_total = 0,
.count_isr_total = 0,
.count_isr_rollover = 0,
.count_isr_handler_call = 0,
.count_isr_unset = 0,
};
#define HWTIMER_STATS_INC(x) (hwtimer_stats.x++)
#else
#define HWTIMER_STATS_INC(x)
#endif /* HWTIMER_STATS */
#define LPTMR_MAXTICKS (0x0000FFFF)
/* Minimum number of ticks when overflowing. This number should be calibrated
* against the maximum run time of the LPTMR ISR in order to avoid missing a
* target. */
#define LPTMR_ISR_TICK_MARGIN (1)
/* Convenience macro to get a reference to the TCF flag in the status register */
#define LPTIMER_TCF (BITBAND_REG32(LPTIMER_DEV->CSR, LPTMR_CSR_TCF_SHIFT))
#ifndef LPTIMER_CNR_NEEDS_LATCHING
#warning LPTIMER_CNR_NEEDS_LATCHING is not defined in cpu_conf.h! Defaulting to 1
#define LPTIMER_CNR_NEEDS_LATCHING 1
#endif
typedef struct {
uint32_t counter32b;
uint32_t cmr32b;
uint32_t diff;
} hwtimer_stimer32b_t;
static hwtimer_stimer32b_t stimer;
/**
* @brief Reference to the hwtimer callback
*/
void (*timeout_handler)(int);
#if LPTIMER_CNR_NEEDS_LATCHING
/* read the CNR register */
inline static uint32_t lptmr_get_cnr(void)
{
uint32_t cnr;
/* Write some garbage to CNR to latch the current value */
asm volatile (
/* write garbage to CNR to latch the value, it does not matter what the
* value of r0 is. Testing shows that the write must be 32 bit wide or
* we will get garbage when reading back CNR. */
"str %[CNR], [%[CNR_p], #0]\n"
"ldr %[CNR], [%[CNR_p], #0]\n" /* Read CNR */
: /* Output variables */
[CNR] "=&r" (cnr)
: /* Input variables */
[CNR_p] "r" (&(LPTIMER_DEV->CNR))
: /* Clobbered registers */
);
return cnr;
}
/* Update the CMR register and return the old CNR before the reset */
inline static uint32_t lptmr_update_cmr(uint32_t cmr)
{
/* Optimized version for CPUs which support latching the LPTMR value */
uint32_t cnr;
asm volatile (
/* Prepare On/Off values in registers r6, r7 */
"mov r6, #0\n"
"mov r7, #1\n"
/* Any ticks that occur between the below write to CNR_p and the write
* to TEN below will be lost, try to keep it short to minimize the
* risk. */
/* write garbage to CNR to latch the value, it does not matter what the
* value of r7 is. Testing shows that the write must be 32 bit wide or
* we will get garbage when reading back CNR. */
"str r7, [%[CNR_p], #0]\n"
"ldr %[CNR], [%[CNR_p], #0]\n" /* Read CNR */
"strh r6, [%[TEN], #0]\n" /* disable timer */
"str %[CMR], [%[CMR_p], #0]\n" /* update CMR */
"strh r7, [%[TEN], #0]\n" /* enable timer */
: /* Output variables */
[CNR] "=&r" (cnr)
: /* Input variables */
[TEN] "r" (BITBAND_REGADDR(LPTIMER_DEV->CSR, LPTMR_CSR_TEN_SHIFT)),
[CMR_p] "r" (&(LPTIMER_DEV->CMR)), [CMR] "r" (cmr),
[CNR_p] "r" (&(LPTIMER_DEV->CNR))
: /* Clobbered registers */
"r6", "r7");
/* The reset happens synchronously with regards to the LPTMR clock, this
* means that on the next tick the CNR register will be reset to zero, and
* not until the next tick after that will the CNR register increment, i.e.
* one tick will always be lost.
* In order to keep the hwtimer somewhat in sync with the RTT the user should
* add 1 to the 32 bit software tick counter after each reset of the LPTMR. */
return cnr;
}
#else /* LPTIMER_CNR_NEEDS_LATCHING */
/* read the CNR register */
inline static uint32_t lptmr_get_cnr(void)
{
/* The early revisions of the Kinetis CPUs do not need latching of the CNR
* register. However, this may lead to corrupt values, we read it twice to
* ensure that we got a valid value */
int i;
uint32_t tmp;
uint32_t cnr = LPTIMER_DEV->CNR;
/* you get three retries */
for (i = 0; i < 3; ++i) {
tmp = LPTIMER_DEV->CNR;
if (tmp == cnr) {
return cnr;
}
cnr = tmp;
}
return cnr;
}
inline static uint32_t lptmr_update_cmr(uint32_t cmr)
{
/* Unoptimized version for older CPUs, this will yield a greater timer drift
* over time between the hwtimer_now() and rtt_get_counter() than the
* optimized version above. */
uint32_t cnr = lptmr_get_cnr();
BITBAND_REG32(LPTIMER_DEV->CSR, LPTMR_CSR_TEN_SHIFT) = 1;
LPTIMER_DEV->CMR = cmr;
BITBAND_REG32(LPTIMER_DEV->CSR, LPTMR_CSR_TEN_SHIFT) = 0;
return cnr;
}
#endif /* LPTIMER_CNR_NEEDS_LATCHING */
inline static void hwtimer_start(void)
{
BITBAND_REG32(LPTIMER_DEV->CSR, LPTMR_CSR_TEN_SHIFT) = 1;
}
void hwtimer_arch_init(void (*handler)(int), uint32_t fcpu)
{
(void) fcpu; /* fcpu does not affect the Low power timer module frequency */
timeout_handler = handler;
/* unlock LPTIMER_DEV */
LPTIMER_CLKEN();
/* set lptmr's IRQ priority */
NVIC_SetPriority(LPTIMER_IRQ_CHAN, LPTIMER_IRQ_PRIO);
/* reset lptmr */
LPTIMER_DEV->CSR = 0;
switch (LPTIMER_CLKSRC) {
case LPTIMER_CLKSRC_MCGIRCLK:
/* Select MCGIRCLK as clock source */
LPTIMER_DEV->PSR = LPTMR_PSR_PRESCALE(LPTIMER_CLK_PRESCALE) | LPTMR_PSR_PCS(0);
break;
case LPTIMER_CLKSRC_OSCERCLK:
/* Select OSCERCLK(4 MHz) as clock source */
LPTIMER_DEV->PSR = LPTMR_PSR_PRESCALE(LPTIMER_CLK_PRESCALE) | LPTMR_PSR_PCS(3);
break;
case LPTIMER_CLKSRC_ERCLK32K:
/* Select rtc oscillator output as clock source for ERCLK32K, */
/* it needs functioning RTC module and driver. */
SIM->SOPT1 &= ~(SIM_SOPT1_OSC32KSEL_MASK);
SIM->SOPT1 |= SIM_SOPT1_OSC32KSEL(2);
/* select ERCLK32K as clock source for lptmr0 */
LPTIMER_DEV->PSR = LPTMR_PSR_PBYP_MASK | LPTMR_PSR_PCS(2);
break;
case LPTIMER_CLKSRC_LPO:
default:
/* select LPO as clock source (1 kHz)*/
LPTIMER_DEV->PSR = LPTMR_PSR_PBYP_MASK | LPTMR_PSR_PCS(1);
}
LPTIMER_DEV->CMR = (uint16_t)(LPTMR_MAXTICKS);
/* enable LPTMR interrupt */
LPTIMER_DEV->CSR = LPTMR_CSR_TIE_MASK;
stimer.counter32b = 0;
stimer.cmr32b = 0;
stimer.diff = 0;
hwtimer_arch_enable_interrupt();
hwtimer_start();
}
void hwtimer_arch_enable_interrupt(void)
{
NVIC_EnableIRQ(LPTIMER_IRQ_CHAN);
}
void hwtimer_arch_disable_interrupt(void)
{
NVIC_DisableIRQ(LPTIMER_IRQ_CHAN);
}
void hwtimer_arch_set(unsigned long offset, short timer)
{
(void)timer; /* we only support one timer */
unsigned mask = disableIRQ();
HWTIMER_STATS_INC(count_set_total);
/* it is important that we don't get interrupted between stopping and
* starting the timer again in order to not increase the risk of dropping
* any ticks */
stimer.diff = offset;
if (stimer.diff > LPTMR_MAXTICKS) {
stimer.diff = LPTMR_MAXTICKS;
}
uint32_t diff = stimer.diff;
uint32_t cnr = lptmr_update_cmr(diff);
stimer.counter32b += cnr;
/* The reset in lptmr_update_cmr above happens synchronously and takes
* one LPTMR clock cycle, add the lost tick to the counter to
* compensate. */
stimer.counter32b += 1;
stimer.cmr32b = stimer.counter32b + offset;
restoreIRQ(mask);
DEBUG("cntr: %lu, cmr: %lu, diff: %lu\n", stimer.counter32b, stimer.cmr32b, stimer.diff);
}
void hwtimer_arch_set_absolute(unsigned long value, short timer)
{
unsigned long offset = value - (stimer.counter32b + lptmr_get_cnr());
HWTIMER_STATS_INC(count_set_absolute);
return hwtimer_arch_set(offset, timer);
}
void hwtimer_arch_unset(short timer)
{
(void)timer; /* we only support one timer */
unsigned mask = disableIRQ();
HWTIMER_STATS_INC(count_unset_total);
stimer.diff = 0;
restoreIRQ(mask);
}
unsigned long hwtimer_arch_now(void)
{
return (unsigned int)((lptmr_get_cnr() + stimer.counter32b));
}
void isr_lptmr0(void)
{
/* The timer counter is reset to 0 when the compare value is hit, add the
* compare value to the 32 bit counter. Add 1 for counting the 0'th tick as
* well (TCF asserts when CNR equals CMR and the counter increases) */
stimer.counter32b += LPTIMER_DEV->CMR + 1;
HWTIMER_STATS_INC(count_isr_total);
/* We try to keep the timer running so that we don't lose any ticks. */
/* Writing the CMR register is allowed when the timer is running
* only if the TCF flag is asserted, therefore we defer clearing the TCF
* flag until the end of this ISR */
if (stimer.diff != 0) {
if (stimer.cmr32b > stimer.counter32b) {
/* Target time lies in the future, we rolled over and must update
* the compare register */
HWTIMER_STATS_INC(count_isr_rollover);
stimer.diff = stimer.cmr32b - stimer.counter32b;
if (stimer.diff < (lptmr_get_cnr() + LPTMR_ISR_TICK_MARGIN)) {
/* We have already passed the target time after rolling over */
/* This can happen if for example other ISRs delay the execution
* of this ISR */
/* clear timer compare flag (w1c bit) */
LPTIMER_TCF = 1;
stimer.diff = 0;
timeout_handler(0);
} else {
if (stimer.diff > LPTMR_MAXTICKS) {
/* Target time is too far away, we will have to roll over once
* more. */
stimer.diff = LPTMR_MAXTICKS;
}
LPTIMER_DEV->CMR = stimer.diff;
/* clear compare flag (w1c bit) */
LPTIMER_TCF = 1;
}
} else {
HWTIMER_STATS_INC(count_isr_handler_call);
/* clear compare flag (w1c bit) */
LPTIMER_TCF = 1;
/* Disable callback by setting diff=0 */
stimer.diff = 0;
timeout_handler(0);
}
} else {
HWTIMER_STATS_INC(count_isr_unset);
/* standby run to keep hwtimer_now increasing */
LPTIMER_DEV->CMR = LPTMR_MAXTICKS;
/* clear compare flag (w1c bit) */
LPTIMER_TCF = 1;
}
if (sched_context_switch_request) {
thread_yield();
}
}

113
cpu/kinetis_common/include/hwtimer_cpu.h
View File

@ -1,113 +0,0 @@
/*
* Copyright (C) 2015 PHYTEC Messtechnik GmbH
*
* This file is subject to the terms and conditions of the GNU Lesser General
* Public License v2.1. See the file LICENSE in the top level directory for more
* details.
*/
/**
* @defgroup cpu_kinetis_common_hwtimer Kinetis hwtimer
* @ingroup cpu_kinetis_common
* @brief Driver uses Freescale Low Power Timer lptmr0.
* There are four clock sources available:
*
* LPTIMER_CLKSRC_MCGIRCLK - slow or fast internal reference clock
* LPTIMER_CLKSRC_LPO - PMC 1kHz output
* LPTIMER_CLKSRC_ERCLK32K - OSC32KCLK or the RTC clock
* LPTIMER_CLKSRC_OSCERCLK - system oscillator output
*
* Tested clock sources:
*
* LPO - 1kHz
* RTC - 32768Hz
*
* Possibly, additional settings in System Integration Module are necessary.
* Please consult the Reference Manual of your MCU for proper clock settings.
*
* ### LPTMR Configuration Example (for cpu_conf.h) ###
*
* #define LPTIMER_CLKSRC LPTIMER_CLKSRC_LPO
* #define LPTIMER_CLKEN() (SIM->SCGC5 |= SIM_SCGC5_LPTMR_MASK)
* #define LPTIMER_CLKDIS() (SIM->SCGC5 &= ~SIM_SCGC5_PTMR_MASK)
* #define LPTIMER_CNR_NEEDS_LATCHING 1
*
* Optional settings:
*
* #define LPTIMER_DEV LPTMR0
* #define LPTIMER_IRQ_PRIO 1
* #define LPTIMER_IRQ_CHAN LPTMR0_IRQn
* @{
* @file
* @brief Interface definition for the Kinetis hwtimer driver.
*
* @author Johann Fischer <j.fischer@phytec.de>
*/
#ifndef __HWTIMER_CPU_H
#define __HWTIMER_CPU_H
#include "cpu_conf.h"
#ifdef __cplusplus
extern "C"
{
#endif
/**
* @name Clock settings for the lptmr timer
*/
#define LPTIMER_CLKSRC_MCGIRCLK 0 /**< internal reference clock (4MHz) */
#define LPTIMER_CLKSRC_LPO 1 /**< PMC 1kHz output */
#define LPTIMER_CLKSRC_ERCLK32K 2 /**< RTC clock 32768Hz */
#define LPTIMER_CLKSRC_OSCERCLK 3 /**< system oscillator output, clock from RF-Part */
#ifndef LPTIMER_CLKSRC
#define LPTIMER_CLKSRC LPTIMER_CLKSRC_LPO /**< default clock source */
#endif
#if (LPTIMER_CLKSRC == LPTIMER_CLKSRC_MCGIRCLK)
#define LPTIMER_CLK_PRESCALE 1
#define LPTIMER_SPEED 1000000
#elif (LPTIMER_CLKSRC == LPTIMER_CLKSRC_OSCERCLK)
#define LPTIMER_CLK_PRESCALE 1
#define LPTIMER_SPEED 1000000
#elif (LPTIMER_CLKSRC == LPTIMER_CLKSRC_ERCLK32K)
#define LPTIMER_CLK_PRESCALE 0
#define LPTIMER_SPEED 32768
#else
#define LPTIMER_CLK_PRESCALE 0
#define LPTIMER_SPEED 1000
#endif
#ifndef LPTIMER_DEV
/** default Low Power Timer device */
#define LPTIMER_DEV LPTMR0
#endif
#ifndef LPTIMER_IRQ_PRIO
/** IRQ priority for hwtimer interrupts */
#define LPTIMER_IRQ_PRIO 1
#endif
#ifndef LPTIMER_IRQ_CHAN
/** IRQ channel for hwtimer interrupts */
#define LPTIMER_IRQ_CHAN LPTMR0_IRQn
#endif
/**
* @name Hardware timer configuration
* @{
*/
#define HWTIMER_MAXTIMERS 1 /**< the CPU implementation supports 1 HW timer */
#define HWTIMER_MAXTICKS (0xFFFFFFFF) /**< simulating 32-bit timer behavior */
#define HWTIMER_SPEED LPTIMER_SPEED /**< speed depends on clock source and prescale */
/** @} */
#ifdef __cplusplus
}
#endif
#endif /* __HWTIMER_CPU_H */
/** @} */

2
cpu/kinetis_common/pwm.c
View File

@ -31,8 +31,6 @@
#include "periph/pwm.h"
#include "periph_conf.h"
#include "hwtimer.h"
/* ignore file in case no PWM devices are defined */
#if PWM_NUMOF

3
cpu/lm4f120/Makefile.include
View File

@ -1,7 +1,4 @@
export CPU_ARCH = cortex-m4f
# use hwtimer compatibility module
USEMODULE += hwtimer_compat
include $(RIOTCPU)/Makefile.include.cortexm_common
include $(RIOTCPU)/stellaris_common/Makefile

1
cpu/lm4f120/include/cpu_conf.h
View File

@ -45,7 +45,6 @@ extern "C" {
#include "stellaris_periph/uart.h"
#include "stellaris_periph/fpu.h"
#include "stellaris_periph/rom.h"
#include "hwtimer_cpu.h"
#include "periph/uart.h"
#ifdef CPU_MODEL_LM4F120H5QR

42
cpu/lm4f120/include/hwtimer_cpu.h
View File

@ -1,42 +0,0 @@
/*
* Copyright (C) 2015 Rakendra Thapa <rakendrathapa@gmail.coa>
*
* This file is subject to the terms and conditions of the GNU Lesser General
* Public License v2.1. See the file LICENSE in the top level directory for more
* details.
*/
/**
* @ingroup cpu_lm4f120
* @{
*
* @file
* @brief CPU specific hwtimer configuration options
*
* @author Rakendra Thapa <rakendrathapa@gmail.com>
*/
#ifndef HWTIMER_CPU_H
#define HWTIMER_CPU_H
#ifdef __cplusplus
extern "C" {
#endif
/**
* @name Hardware timer configuration
* @{
*/
#define HWTIMER_MAXTIMERS 1 /**< the CPU implementation supports 4 HW timers */
#define HWTIMER_SPEED 1000000 /**< the HW timer runs with 1MHz */
#define HWTIMER_MAXTICKS 0xffffffff /**< 32-bit timer */
#define HWTIMER_MSEC (HWTIMER_SPEED/1000)
#define HWTIMER_SEC (HWTIMER_SPEED/1000000)
/**@}*/
#ifdef __cplusplus
}
#endif
#endif /* HWTIMER_CPU_H */
/** @} */

3
cpu/lpc1768/Makefile.include
View File

@ -1,6 +1,3 @@
export CPU_ARCH = cortex-m3
# use hwtimer compatibility module
USEMODULE += hwtimer_compat
include $(RIOTCPU)/Makefile.include.cortexm_common

2
cpu/lpc1768/include/cpu_conf.h
View File

@ -13,7 +13,7 @@
* @{
*
* @file
* @brief CPU specific hwtimer configuration options
* @brief CPU specific configuration options
*
* @author Hauke Petersen <hauke.peterse@fu-berlin.de>
*/

40
cpu/lpc1768/include/hwtimer_cpu.h
View File

@ -1,40 +0,0 @@
/*
* Copyright (C) 2014 Freie Universität Berlin
*
* This file is subject to the terms and conditions of the GNU Lesser General
* Public License v2.1. See the file LICENSE in the top level directory for more
* details.
*/
/**
* @ingroup cpu_lpc1768
* @{
*
* @file
* @brief CPU specific hwtimer configuration options
*
* @author Hauke Petersen <hauke.peterse@fu-berlin.de>
*/
#ifndef __HWTIMER_CPU_H
#define __HWTIMER_CPU_H
#ifdef __cplusplus
extern "C" {
#endif
/**
* @name Hardware timer configuration
* @{
*/
#define HWTIMER_MAXTIMERS 4 /**< the CPU implementation supports 4 HW timers */
#define HWTIMER_SPEED 1000000 /**< the HW timer runs with 1MHz */
#define HWTIMER_MAXTICKS (0xFFFFFFFF) /**< 32-bit timer */
/** @} */
#ifdef __cplusplus
}
#endif
#endif /* __HWTIMER_CPU_H */
/** @} */

2
cpu/lpc2387/Makefile.include
View File

@ -2,4 +2,4 @@ INCLUDES += -I$(RIOTCPU)/lpc2387/include
include $(RIOTCPU)/arm7_common/Makefile.include
USEMODULE += arm7_common periph periph_common bitfield newlib hwtimer_compat
USEMODULE += arm7_common periph periph_common bitfield newlib

6
cpu/lpc2387/lpc2387-adc.c
View File

@ -25,7 +25,7 @@
#define ENABLE_DEBUG (0)
#include "debug.h"
#if ENABLE_DEBUG
#include "hwtimer.h"
#include "xtimer.h"
#endif
/*---------------------------------------------------------------------------*/
@ -109,12 +109,12 @@ uint16_t adc_read(uint8_t channel)
/* switch channel, start A/D convert */
AD0CR &= 0xFFFFFF00;
#if ENABLE_DEBUG
t1 = hwtimer_now();
t1 = xtimer_now();
#endif
AD0CR |= (1 << 24) | (1 << channel);
#if ENABLE_DEBUG
t2 = hwtimer_now();
t2 = xtimer_now();
#endif
while (1) {

26
cpu/lpc2387/mci/lpc2387-mci.c
View File

@ -15,13 +15,13 @@
#include <string.h>
#include "lpc23xx.h"
#include "VIC.h"
#include "hwtimer.h"
#include "xtimer.h"
#include "diskio.h"
#define ENABLE_DEBUG (0)
#include "debug.h"
extern unsigned long hwtimer_now(void);
extern unsigned long xtimer_now(void);
/* --- MCI configurations --- */
#define N_BUF 4 /* Block transfer FIFO depth (>= 2) */
@ -334,7 +334,7 @@ static void power_on(void)
MCI_POWER = 0x01; /* Power on */
//for (Timer[0] = 10; Timer[0]; ) ; /* 10ms */
hwtimer_wait(1000);
xtimer_usleep(1000);
MCI_POWER = 0x03; /* Enable signals */
}
@ -415,12 +415,12 @@ static int send_cmd(unsigned int idx, unsigned long arg, unsigned int rt, unsign
MCI_COMMAND = mc; /* Initiate command transaction */
//Timer[1] = 100;
uint32_t timerstart = hwtimer_now();
uint32_t timerstart = xtimer_now();
while (1) { /* Wait for end of the cmd/resp transaction */
//if (!Timer[1]) return 0;
if (hwtimer_now() - timerstart > 10000) {
if (xtimer_now() - timerstart > 10000) {
return 0;
}
@ -477,10 +477,10 @@ static int wait_ready(unsigned short tmr)
{
unsigned long rc;
uint32_t stoppoll = hwtimer_now() + tmr * 100;
uint32_t stoppoll = xtimer_now() + tmr * 100;
bool bBreak = false;
while (hwtimer_now() < stoppoll/*Timer[0]*/) {
while (xtimer_now() < stoppoll/*Timer[0]*/) {
if (send_cmd(CMD13, (unsigned long) CardRCA << 16, 1, &rc) && ((rc & 0x01E00) == 0x00800)) {
bBreak = true;
break;
@ -535,12 +535,12 @@ DSTATUS MCI_initialize(void)
power_off();
hwtimer_wait(HWTIMER_TICKS(1000));
xtimer_usleep(1000);
power_on(); /* Force socket power on */
MCI_CLOCK = 0x100 | (PCLK / MCLK_ID / 2 - 1); /* Set MCICLK = MCLK_ID */
//for (Timer[0] = 2; Timer[0]; );
hwtimer_wait(250);
xtimer_usleep(250);
send_cmd(CMD0, 0, 0, NULL); /* Enter idle state */
CardRCA = 0;
@ -548,7 +548,7 @@ DSTATUS MCI_initialize(void)
/*---- Card is 'idle' state ----*/
/* Initialization timeout of 1000 msec */
uint32_t start = hwtimer_now();
uint32_t start = xtimer_now();
/* SDC Ver2 */
if (send_cmd(CMD8, 0x1AA, 1, resp) && (resp[0] & 0xFFF) == 0x1AA) {
@ -557,7 +557,7 @@ DSTATUS MCI_initialize(void)
do { /* Wait while card is busy state (use ACMD41 with HCS bit) */
/* This loop will take a time. Insert wai_tsk(1) here for multitask envilonment. */
if (hwtimer_now() > start + 1000000/*!Timer[0]*/) {
if (xtimer_now() > start + 1000000/*!Timer[0]*/) {
DEBUG("%s, %d: Timeout #1\n", __FILE__, __LINE__);
goto di_fail;
}
@ -582,8 +582,8 @@ DSTATUS MCI_initialize(void)
DEBUG("%s, %d: %lX\n", __FILE__, __LINE__, resp[0]);
/* This loop will take a time. Insert wai_tsk(1) here for multitask envilonment. */
if (hwtimer_now() > start + 1000000/*!Timer[0]*/) {
DEBUG("now: %lu, started at: %lu\n", hwtimer_now(), start);
if (xtimer_now() > start + 1000000/*!Timer[0]*/) {
DEBUG("now: %lu, started at: %lu\n", xtimer_now(), start);
DEBUG("%s, %d: Timeout #2\n", __FILE__, __LINE__);
goto di_fail;
}

46
cpu/msp430-common/include/hwtimer_cpu.h
View File

@ -1,46 +0,0 @@
/*
* Copyright (C) 2014 INRIA
* 2014, 2015 Freie Universität Berlin
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @ingroup cpu_msp430-common
* @{
*
* @file
* @brief Hardware timer configuration for MSP430 based CPUs
*
* @author Oliver Hahm <oliver.hahm@inria.fr>
* @author Kévin Roussel <Kevin.Roussel@inria.fr>
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
*
*/
#ifndef HWTIMER_CPU_H_
#define HWTIMER_CPU_H_
#include "board.h"
#include "periph_conf.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief Hardware timer configuration
* @{
*/
#define HWTIMER_MAXTIMERS (TIMER_CHAN)
#define HWTIMER_SPEED (F_RC_OSCILLATOR)
#define HWTIMER_MAXTICKS (0x0000FFFF)
/** @} */
#ifdef __cplusplus
}
#endif
#endif /* HWTIMER_CPU_H_ */

2
cpu/msp430fxyz/Makefile.include
View File

@ -3,5 +3,5 @@ INCLUDES += -I$(RIOTCPU)/msp430fxyz/include/
include $(RIOTCPU)/msp430-common/Makefile.include
USEMODULE += periph
USEMODULE += hwtimer_compat
export USEMODULE

2
cpu/native/Makefile.include
View File

@ -5,4 +5,4 @@ ifeq ($(BUILDOSXNATIVE),1)
export NATIVEINCLUDES += -I$(RIOTBASE)/sys/malloc/include
endif
export USEMODULE += periph hwtimer_compat
export USEMODULE += periph

35
cpu/native/include/hwtimer_cpu.h
View File

@ -1,35 +0,0 @@
/**
* Native CPU hwtimer_cpu configuration
*
* Copyright (C) 2013 Ludwig Ortmann <ludwig.ortmann@fu-berlin.de>
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*
* @{
* @ingroup native_hwtimer
* @file
* @author Ludwig Ortmann <ludwig.ortmann@fu-berlin.de>
* @}
*/
#include "periph_conf.h"
#ifndef HWTIMER_CPU_H_
#define HWTIMER_CPU_H_
#ifdef __cplusplus
extern "C" {
#endif
#define HWTIMER_MAXTIMERS 1
#define HWTIMER_SPEED 1000000
#define HWTIMER_MAXTICKS (0xFFFFFFFF)
#define HWTIMER_SPIN_BARRIER NATIVE_TIMER_MIN_RES
#ifdef __cplusplus
}
#endif
#endif /* HWTIMER_CPU_H_ */

1
cpu/native/include/native_internal.h
View File

@ -65,7 +65,6 @@ typedef void (*_native_callback_t)(void);
*/
void native_cpu_init(void);
void native_interrupt_init(void);
extern void native_hwtimer_pre_init(void);
void native_irq_handler(void);
extern void _native_sig_leave_tramp(void);

8
cpu/native/include/periph_conf.h
View File

@ -48,8 +48,12 @@
#define TIMER_NUMOF (1U)
#define TIMER_0_EN 1
/** @def set TIMER0 for hwtimer wrapper */
#define HW_TIMER TIMER_0
/**
* @brief xtimer configuration
* @{
*/
#define XTIMER_OVERHEAD 14
#define XTIMER_USLEEP_UNTIL_OVERHEAD 1
/** @} */
#ifdef __cplusplus

4
cpu/native/periph/timer.c
View File

@ -6,7 +6,7 @@
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*
* @ingroup hwtimer
* @ingroup timer
* @ingroup native_cpu
* @{
* @author Ludwig Ortmann <ludwig.ortmann@fu-berlin.de>
@ -17,7 +17,7 @@
* Uses POSIX realtime clock and POSIX itimer to mimic hardware.
*
* This is based on native's hwtimer implementation by Ludwig Ortmann.
* I removed the multiplexing, as wtimer does the same. (kaspar)
* I removed the multiplexing, as xtimer does the same. (kaspar)
*
* @}
*/

3
cpu/nrf51/Makefile.include
View File

@ -1,6 +1,3 @@
export CPU_ARCH = cortex-m0
# use hwtimer compatibility module
USEMODULE += hwtimer_compat
include $(RIOTCPU)/Makefile.include.cortexm_common

41
cpu/nrf51/include/hwtimer_cpu.h
View File

@ -1,41 +0,0 @@
/*
* Copyright (C) 2014 Freie Universität Berlin
*
* This file is subject to the terms and conditions of the GNU Lesser General
* Public License v2.1. See the file LICENSE in the top level directory for more
* details.
*/
/**
* @ingroup cpu_nrf51822
* @{
*
* @file
* @brief CPU specific hwtimer configuration options
*
* @author Hauke Petersen <hauke.peterse@fu-berlin.de>
*/
#ifndef __HWTIMER_CPU_H
#define __HWTIMER_CPU_H
#ifdef __cplusplus
extern "C" {
#endif
/**
* @name Hardware timer configuration
* @{
*/
#define HWTIMER_MAXTIMERS 3 /**< the CPU implementation supports 3 HW timers */
#define HWTIMER_SPEED 1000000 /**< the HW timer runs with 1MHz */
#define HWTIMER_MAXTICKS (0xFFFFFF) /**< 24-bit timer -> see PAN note */
/** @} */
#ifdef __cplusplus
}
#endif
#endif /* __HWTIMER_CPU_H */
/** @} */

3
cpu/sam3/Makefile.include
View File

@ -1,8 +1,5 @@
export CPU_ARCH = cortex-m3
# use hwtimer compatibility module
USEMODULE += hwtimer_compat
# include common SPI functions
USEMODULE += periph_common

41
cpu/sam3/include/hwtimer_cpu.h
View File

@ -1,41 +0,0 @@
/*
* Copyright (C) 2014 Freie Universität Berlin
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @ingroup cpu_sam3
* @{
*
* @file
* @brief CPU specific hwtimer configuration options
*
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
*/
#ifndef __HWTIMER_CPU_H
#define __HWTIMER_CPU_H
#ifdef __cplusplus
extern "C" {
#endif
/**
* @name Hardware timer configuration
* @{
*/
#define HWTIMER_MAXTIMERS 6 /**< the CPU implementation supports 3 HW timers */
#define HWTIMER_SPEED 1000000 /**< the HW timer runs with 1MHz */
#define HWTIMER_MAXTICKS (0xFFFFFFFF) /**< 32-bit timer */
/** @} */
#ifdef __cplusplus
}
#endif
#endif /* __HWTIMER_CPU_H */
/** @} */

3
cpu/samd21/Makefile.include
View File

@ -3,9 +3,6 @@ export CPU_ARCH = cortex-m0plus
# this CPU implementation doesn't use CMSIS initialisation
export CFLAGS += -DDONT_USE_CMSIS_INIT
# use the hwtimer compatibility layer
USEMODULE += hwtimer_compat
# use common periph functions
USEMODULE += periph_common

40
cpu/samd21/include/hwtimer_cpu.h
View File

@ -1,40 +0,0 @@
/*
* Copyright (C) 2014 Freie Universität Berlin
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @ingroup cpu_samd21
* @{
*
* @file
* @brief CPU specific hwtimer configuration options
*
* @author Thomas Eichinger <thomas.eichinger@fu-berlin.de>
*/
#ifndef __HWTIMER_CPU_H
#define __HWTIMER_CPU_H
#ifdef __cplusplus
extern "C" {
#endif
/**
* @name Hardware timer configuration
* @{
*/
#define HWTIMER_MAXTIMERS 2 /**< the CPU implementation supports 1 HW timer */
#define HWTIMER_SPEED (1000000U) /**< the HW timer runs with 1MHz */
#define HWTIMER_MAXTICKS (0xFFFFFFFF) /**< 32-bit timer */
/** @} */
#ifdef __cplusplus
}
#endif
#endif /* __HWTIMER_CPU_H */
/** @} */

3
cpu/saml21/Makefile.include
View File

@ -3,9 +3,6 @@ export CPU_ARCH = cortex-m0plus
# this CPU implementation doesn't use CMSIS initialisation
export CFLAGS += -DDONT_USE_CMSIS_INIT
# use the hwtimer compatibility module
USEMODULE += hwtimer_compat
# use common periph functions
USEMODULE += periph_common

40
cpu/saml21/include/hwtimer_cpu.h
View File

@ -1,40 +0,0 @@
/*
* Copyright (C) 2014 Freie Universität Berlin
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @ingroup cpu_saml21
* @{
*
* @file
* @brief CPU specific hwtimer configuration options
*
* @author Thomas Eichinger <thomas.eichinger@fu-berlin.de>
*/
#ifndef __HWTIMER_CPU_H
#define __HWTIMER_CPU_H
#ifdef __cplusplus
extern "C" {
#endif
/**
* @name Hardware timer configuration
* @{
*/
#define HWTIMER_MAXTIMERS 1 /**< the CPU implementation supports 1 HW timer */
#define HWTIMER_SPEED (1000000U) /**< the HW timer runs with 1MHz */
#define HWTIMER_MAXTICKS (0xFFFFFFFF) /**< 32-bit timer */
/** @} */
#ifdef __cplusplus
}
#endif
#endif /* __HWTIMER_CPU_H */
/** @} */

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