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cpu/stm32f1: adapt gpio driver and usage to CMSIS struct

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This commit is contained in:
Alexandre Abadie 2020-05-26 16:26:49 +02:00
parent 1a8f4d4f25
commit cc9219c96e
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GPG Key ID: 1C919A403CAE1405
2 changed files with 14 additions and 14 deletions
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16
cpu/stm32/cpu_init.c
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@ -101,16 +101,16 @@ static void _gpio_init_ain(void)
switch (i) {
/* preserve JTAG pins on PORTA and PORTB */
case 0:
port->CR[0] = GPIO_CRL_CNF;
port->CR[1] = GPIO_CRH_CNF & 0x000FFFFF;
port->CRL = GPIO_CRL_CNF;
port->CRH = GPIO_CRH_CNF & 0x000FFFFF;
break;
case 1:
port->CR[0] = GPIO_CRL_CNF & 0xFFF00FFF;
port->CR[1] = GPIO_CRH_CNF;
port->CRL = GPIO_CRL_CNF & 0xFFF00FFF;
port->CRH = GPIO_CRH_CNF;
break;
default:
port->CR[0] = GPIO_CRL_CNF;
port->CR[1] = GPIO_CRH_CNF;
port->CRL = GPIO_CRL_CNF;
port->CRH = GPIO_CRH_CNF;
break;
}
#else /* ! defined(CPU_FAM_STM32F1) */
@ -130,8 +130,8 @@ static void _gpio_init_ain(void)
}
else {
#if defined(CPU_FAM_STM32F1)
port->CR[0] = GPIO_CRL_CNF;
port->CR[1] = GPIO_CRH_CNF;
port->CRL = GPIO_CRL_CNF;
port->CRH = GPIO_CRH_CNF;
#else
port->MODER = 0xFFFFFFFF;
#endif

12
cpu/stm32/periph/gpio_f1.c
View File

@ -89,8 +89,8 @@ int gpio_init(gpio_t pin, gpio_mode_t mode)
periph_clk_en(APB2, (RCC_APB2ENR_IOPAEN << _port_num(pin)));
/* set pin mode */
port->CR[pin_num >> 3] &= ~(0xf << ((pin_num & 0x7) * 4));
port->CR[pin_num >> 3] |= ((mode & MODE_MASK) << ((pin_num & 0x7) * 4));
*(uint32_t *)(&port->CRL + (pin_num >> 3)) &= ~(0xf << ((pin_num & 0x7) * 4));
*(uint32_t *)(&port->CRL + (pin_num >> 3)) |= ((mode & MODE_MASK) << ((pin_num & 0x7) * 4));
/* set ODR */
if (mode == GPIO_IN_PU)
@ -109,8 +109,8 @@ void gpio_init_af(gpio_t pin, gpio_af_t af)
/* enable the clock for the selected port */
periph_clk_en(APB2, (RCC_APB2ENR_IOPAEN << _port_num(pin)));
/* configure the pin */
port->CR[pin_num >> 3] &= ~(0xf << ((pin_num & 0x7) * 4));
port->CR[pin_num >> 3] |= (af << ((pin_num & 0x7) * 4));
*(uint32_t *)(&port->CRL + (pin_num >> 3)) &= ~(0xf << ((pin_num & 0x7) * 4));
*(uint32_t *)(&port->CRL + (pin_num >> 3)) |= (af << ((pin_num & 0x7) * 4));
}
void gpio_init_analog(gpio_t pin)
@ -120,7 +120,7 @@ void gpio_init_analog(gpio_t pin)
/* map the pin as analog input */
int pin_num = _pin_num(pin);
_port(pin)->CR[pin_num >= 8] &= ~(0xfl << (4 * (pin_num - ((pin_num >= 8) * 8))));
*(uint32_t *)(&_port(pin)->CRL + (pin_num >= 8)) &= ~(0xfl << (4 * (pin_num - ((pin_num >= 8) * 8))));
}
int gpio_read(gpio_t pin)
@ -128,7 +128,7 @@ int gpio_read(gpio_t pin)
GPIO_TypeDef *port = _port(pin);
int pin_num = _pin_num(pin);
if (port->CR[pin_num >> 3] & (0x3 << ((pin_num & 0x7) << 2))) {
if (*(uint32_t *)(&port->CRL + (pin_num >> 3)) & (0x3 << ((pin_num & 0x7) << 2))) {
/* pin is output */
return (port->ODR & (1 << pin_num));
}