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https://github.com/RIOT-OS/RIOT.git
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board/cpu: added pwm driver for stm32f4discovery
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@ -148,33 +148,40 @@
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* @name PWM configuration
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* @{
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*/
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#define PWM_NUMOF (0U) /* TODO !!!!!!! */
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#define PWM_0_EN 0
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#define PWM_1_EN 0
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#define PWM_NUMOF (2U)
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#define PWM_0_EN 1
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#define PWM_1_EN 1
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#define PWM_MAX_CHANNELS 4
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/* PWM 0 device configuration */
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#define PWM_0_DEV TIM1
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#define PWM_0_CHANNELS 4
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#define PWM_0_CLK (168000000U)
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#define PWM_0_CLKEN() (RCC->APB2ENR |= RCC_APB2ENR_TIM1EN)
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#define PWM_0_CLKDIS() (RCC->APB2ENR &= ~RCC_APB2ENR_TIM1EN)
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/* PWM 0 pin configuration */
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#define PWM_0_PORT
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#define PWM_0_PINS
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#define PWM_0_PORT_CLKEN()
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#define PWM_0_CH1_AFCFG()
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#define PWM_0_CH2_AFCFG()
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#define PWM_0_CH3_AFCFG()
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#define PWM_0_CH4_AFCFG()
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#define PWM_0_PORT GPIOE
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#define PWM_0_PORT_CLKEN() (RCC->AHB1ENR |= RCC_AHB1ENR_GPIOEEN)
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#define PWM_0_PIN_CH0 9
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#define PWM_0_PIN_CH1 11
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#define PWM_0_PIN_CH2 13
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#define PWM_0_PIN_CH3 14
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#define PWM_0_PIN_AF 1
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/* PWM 1 device configuration */
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#define PWM_1_DEV TIM3
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#define PWM_1_CHANNELS 4
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#define PWM_1_CHANNELS 3
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#define PWM_1_CLK (84000000U)
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#define PWM_1_CLKEN() (RCC->APB1ENR |= RCC_APB1ENR_TIM3EN)
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#define PWM_1_CLKDIS() (RCC->APB1ENR &= ~RCC_APB1ENR_TIM3EN)
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/* PWM 1 pin configuration */
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#define PWM_1_PORT
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#define PWM_1_PINS
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#define PWM_1_PORT_CLKEN()
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#define PWM_1_CH1_AFCFG()
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#define PWM_1_CH2_AFCFG()
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#define PWM_1_CH3_AFCFG()
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#define PWM_1_CH4_AFCFG()
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#define PWM_1_PORT GPIOB
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#define PWM_1_PORT_CLKEN() (RCC->AHB1ENR |= RCC_AHB1ENR_GPIOBEN)
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#define PWM_1_PIN_CH0 4
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#define PWM_1_PIN_CH1 5
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#define PWM_1_PIN_CH2 0
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#define PWM_1_PIN_CH3 1
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#define PWM_1_PIN_AF 2
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/** @} */
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242
cpu/stm32f4/periph/pwm.c
Normal file
242
cpu/stm32f4/periph/pwm.c
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@ -0,0 +1,242 @@
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/*
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* Copyright (C) 2014 Freie Universität Berlin
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*
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* This file is subject to the terms and conditions of the GNU Lesser General
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* Public License v2.1. See the file LICENSE in the top level directory for more
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* details.
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*/
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/**
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* @ingroup cpu_stm32f4
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* @{
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*
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* @file
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* @brief Low-level GPIO driver implementation
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*
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* @author Hauke Petersen <mail@haukepetersen.de>
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*
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* @}
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*/
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#include <stdint.h>
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#include <string.h>
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#include "cpu.h"
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#include "periph/pwm.h"
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#include "periph_conf.h"
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/* ignore file in case no PWM devices are defined */
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#if PWM_NUMOF
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int pwm_init(pwm_t dev, pwm_mode_t mode, unsigned int frequency, unsigned int resolution)
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{
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TIM_TypeDef *tim = NULL;
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GPIO_TypeDef *port = NULL;
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uint32_t pins[PWM_MAX_CHANNELS];
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uint32_t af = 0;
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int channels = 0;
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uint32_t pwm_clk = 0;
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pwm_poweron(dev);
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switch (dev) {
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#if PWM_0_EN
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case PWM_0:
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tim = PWM_0_DEV;
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port = PWM_0_PORT;
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pins[0] = PWM_0_PIN_CH0;
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pins[1] = PWM_0_PIN_CH1;
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pins[2] = PWM_0_PIN_CH2;
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pins[3] = PWM_0_PIN_CH3;
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af = PWM_0_PIN_AF;
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channels = PWM_0_CHANNELS;
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pwm_clk = PWM_0_CLK;
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PWM_0_PORT_CLKEN();
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break;
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#endif
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#if PWM_1_EN
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case PWM_1:
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tim = PWM_1_DEV;
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port = PWM_1_PORT;
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pins[0] = PWM_1_PIN_CH0;
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pins[1] = PWM_1_PIN_CH1;
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pins[2] = PWM_1_PIN_CH2;
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pins[3] = PWM_1_PIN_CH3;
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af = PWM_1_PIN_AF;
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channels = PWM_1_CHANNELS;
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pwm_clk = PWM_1_CLK;
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PWM_1_PORT_CLKEN();
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break;
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#endif
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}
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/* setup pins: alternate function */
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for (int i = 0; i < channels; i++) {
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port->MODER &= ~(3 << (pins[i] * 2));
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port->MODER |= (2 << (pins[i] * 2));
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if (pins[i] < 8) {
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port->AFR[0] &= ~(0xf << (pins[i] * 4));
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port->AFR[0] |= (af << (pins[i] * 4));
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} else {
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port->AFR[1] &= ~(0xf << ((pins[i] - 8) * 4));
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port->AFR[1] |= (af << ((pins[i] - 8) * 4));
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}
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}
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/* reset timer configuration registers */
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tim->CR1 = 0;
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tim->CR2 = 0;
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tim->CCMR1 = 0;
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tim->CCMR2 = 0;
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/* set c/c register to initial 0 */
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tim->CCR1 = 0;
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tim->CCR2 = 0;
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tim->CCR3 = 0;
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tim->CCR4 = 0;
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/* set prescale and auto-reload registers to matching values for resolution and frequency */
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if (resolution > 0xffff || (resolution * frequency) > pwm_clk) {
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return -2;
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}
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tim->PSC = (pwm_clk / (resolution * frequency)) - 1;
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tim->ARR = resolution - 1;
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/* set PWM mode */
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switch (mode) {
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case PWM_LEFT:
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tim->CCMR1 |= (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2 |
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TIM_CCMR1_OC2M_1 | TIM_CCMR1_OC2M_2);
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tim->CCMR2 |= (TIM_CCMR2_OC3M_1 | TIM_CCMR2_OC3M_2 |
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TIM_CCMR2_OC4M_1 | TIM_CCMR2_OC4M_2);
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break;
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case PWM_RIGHT:
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tim->CCMR1 |= (TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2 |
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TIM_CCMR1_OC2M_0 | TIM_CCMR1_OC2M_1 | TIM_CCMR1_OC2M_2);
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tim->CCMR2 |= (TIM_CCMR2_OC3M_0 | TIM_CCMR2_OC3M_1 | TIM_CCMR2_OC3M_2 |
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TIM_CCMR2_OC4M_0 | TIM_CCMR2_OC4M_1 | TIM_CCMR2_OC4M_2);
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break;
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case PWM_CENTER:
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tim->CR1 |= (TIM_CR1_CMS_0 | TIM_CR1_CMS_1);
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break;
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}
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/* enable output on PWM pins */
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tim->CCER = (TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E);
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/* enable PWM outputs */
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tim->BDTR = TIM_BDTR_MOE;
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/* enable timer ergo the PWM generation */
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pwm_start(dev);
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return 0;
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}
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int pwm_set(pwm_t dev, int channel, unsigned int value)
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{
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TIM_TypeDef *tim = NULL;
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switch (dev) {
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#if PWM_0_EN
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case PWM_0:
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tim = PWM_0_DEV;
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break;
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#endif
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#if PWM_1_EN
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case PWM_1:
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tim = PWM_1_DEV;
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break;
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#endif
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}
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/* norm value to maximum possible value */
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if (value > 0xffff) {
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value = 0xffff;
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}
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switch (channel) {
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case 0:
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tim->CCR1 = value;
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break;
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case 1:
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tim->CCR2 = value;
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break;
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case 2:
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tim->CCR3 = value;
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break;
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case 3:
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tim->CCR4 = value;
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break;
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default:
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return -1;
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}
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return 0;
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}
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void pwm_start(pwm_t dev)
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{
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switch (dev) {
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#if PWM_0_EN
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case PWM_0:
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PWM_0_DEV->CR1 |= TIM_CR1_CEN;
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break;
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#endif
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#if PWM_1_EN
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case PWM_1:
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PWM_1_DEV->CR1 |= TIM_CR1_CEN;
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break;
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#endif
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}
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}
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void pwm_stop(pwm_t dev)
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{
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switch (dev) {
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#if PWM_0_EN
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case PWM_0:
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PWM_0_DEV->CR1 &= ~(TIM_CR1_CEN);
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break;
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#endif
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#if PWM_1_EN
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case PWM_1:
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PWM_1_DEV->CR1 &= ~(TIM_CR1_CEN);
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break;
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#endif
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}
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}
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void pwm_poweron(pwm_t dev)
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{
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switch (dev) {
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#if PWM_0_EN
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case PWM_0:
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PWM_0_CLKEN();
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break;
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#endif
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#if PWM_1_EN
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case PWM_1:
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PWM_1_CLKEN();
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break;
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#endif
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}
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}
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void pwm_poweroff(pwm_t dev)
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{
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switch (dev) {
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#if PWM_0_EN
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case PWM_0:
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PWM_0_CLKDIS();
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break;
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#endif
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#if PWM_1_EN
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case PWM_1:
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PWM_1_CLKDIS();
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break;
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#endif
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}
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}
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#endif /* PWM_NUMOF */
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