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cpu/stm32f0: adapted to centralized cpu conf

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This commit is contained in:
Hauke Petersen 2015-05-27 23:07:43 +02:00
parent dfb717c308
commit cb476daff0
5 changed files with 10 additions and 41 deletions
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5
cpu/stm32f0/cpu.c
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@ -28,11 +28,10 @@ static void clock_init(void);
*/ */
void cpu_init(void) void cpu_init(void)
{ {
/* initialize the Cortex-M core */
cortexm_init();
/* initialize the clock system */ /* initialize the clock system */
clock_init(); clock_init();
/* set pendSV interrupt to lowest possible priority */
NVIC_SetPriority(PendSV_IRQn, 0xff);
} }
/** /**

36
cpu/stm32f0/include/cpu_conf.h
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@ -33,32 +33,11 @@ extern "C" {
#endif #endif
/** /**
* @name Kernel configuration * @brief ARM Cortex-M specific CPU configuration
*
* The absolute minimum stack size is 140 byte (68 byte for the tcb + 72 byte
* for a complete context save).
*
* TODO: measure and adjust for the Cortex-M0
* @{ * @{
*/ */
#define THREAD_EXTRA_STACKSIZE_PRINTF (512) #define CPU_DEFAULT_IRQ_PRIO (1U)
#define CPU_IRQ_NUMOF (31U)
#ifndef THREAD_STACKSIZE_DEFAULT
#define THREAD_STACKSIZE_DEFAULT (512)
#endif
#define THREAD_STACKSIZE_IDLE (192)
/** @} */
/**
* @name UART0 buffer size definition for compatibility reasons
*
* TODO: remove once the remodeling of the uart0 driver is done
* @{
*/
#ifndef UART0_BUFSIZE
#define UART0_BUFSIZE (128)
#endif
/** @} */ /** @} */
/** /**
@ -66,15 +45,6 @@ extern "C" {
*/ */
#define CPUID_ID_LEN (12) #define CPUID_ID_LEN (12)
/**
* @brief Definition of different panic modes
*/
typedef enum {
HARD_FAULT, /**< hard fault */
NMI_HANDLER, /**< non maskable interrupt */
DUMMY_HANDLER /**< dummy interrupt handler */
} panic_t;
#ifdef __cplusplus #ifdef __cplusplus
} }
#endif #endif

2
cpu/stm32f0/include/stm32f051x8.h
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@ -85,7 +85,7 @@ typedef enum
/****** Cortex-M0 Processor Exceptions Numbers **************************************************************/ /****** Cortex-M0 Processor Exceptions Numbers **************************************************************/
NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */ HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */
SVC_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */ SVCall_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */
PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */ PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */
SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */ SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */

2
cpu/stm32f0/include/stm32f091xc.h
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@ -84,7 +84,7 @@ typedef enum
/****** Cortex-M0 Processor Exceptions Numbers **************************************************************/ /****** Cortex-M0 Processor Exceptions Numbers **************************************************************/
NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */ HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */
SVC_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */ SVCall_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */
PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */ PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */
SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */ SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */

6
cpu/stm32f0/startup.c
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@ -80,17 +80,17 @@ void reset_handler(void)
*/ */
void dummy_handler(void) void dummy_handler(void)
{ {
core_panic(DUMMY_HANDLER, "DUMMY HANDLER"); core_panic(PANIC_DUMMY_HANDLER, "DUMMY HANDLER");
} }
void isr_nmi(void) void isr_nmi(void)
{ {
core_panic(NMI_HANDLER, "NMI HANDLER"); core_panic(PANIC_NMI_HANDLER, "NMI HANDLER");
} }
void isr_hard_fault(void) void isr_hard_fault(void)
{ {
core_panic(HARD_FAULT, "HARD FAULT"); core_panic(PANIC_HARD_FAULT, "HARD FAULT");
} }
/* Cortex-M specific interrupt vectors */ /* Cortex-M specific interrupt vectors */