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Merge pull request #7469 from MichelRottleuthner/stm32l4_stmclk
stm32l4: implement stmclk interface
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ca38df6960
@ -35,6 +35,12 @@ extern "C" {
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/* 0: no external low speed crystal available,
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* 1: external crystal available (always 32.768kHz) */
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#define CLOCK_LSE (1)
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/* 0: enable MSI only if HSE isn't available
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* 1: always enable MSI (e.g. if USB or RNG is used)*/
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#define CLOCK_MSI_ENABLE (1)
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/* 0: disable Hardware auto calibration with LSE
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* 1: enable Hardware auto calibration with LSE (PLL-mode)*/
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#define CLOCK_MSI_LSE_PLL (1)
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/* give the target core clock (HCLK) frequency [in Hz], maximum: 80MHz */
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#define CLOCK_CORECLOCK (80000000U)
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/* PLL configuration: make sure your values are legit!
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@ -1,6 +1,7 @@
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/*
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* Copyright (C) 2017 Freie Universität Berlin
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* 2017 Inria
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* 2017 HAW-Hamburg
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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@ -16,6 +17,7 @@
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*
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* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
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* @author Alexandre Abadie <alexandre.abadie@inria.fr>
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* @author Michel Rottleuthner <michel.rottleuthner@haw-hamburg.de>
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*/
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#ifndef PERIPH_CONF_H
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@ -34,9 +36,28 @@ extern "C" {
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/* 0: no external high speed crystal available
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* else: actual crystal frequency [in Hz] */
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#define CLOCK_HSE (0)
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#ifndef CLOCK_LSE
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/* 0: no external low speed crystal available,
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* 1: external crystal available (always 32.768kHz) */
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#define CLOCK_LSE (1)
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* 1: external crystal available (always 32.768kHz)
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* This defaults to 0 because hardware revision 'MB1136 C-01' of the nucleo-64
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* board disconnects LSE by default. You may safely set this to 1 on revisions
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* newer than 'MB1136 C-01' */
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#define CLOCK_LSE (0)
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#endif
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/* 0: enable MSI only if HSE isn't available
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* 1: always enable MSI (e.g. if USB or RNG is used)*/
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#define CLOCK_MSI_ENABLE (1)
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#ifndef CLOCK_MSI_LSE_PLL
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/* 0: disable Hardware auto calibration with LSE
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* 1: enable Hardware auto calibration with LSE (PLL-mode)
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* Same as with CLOCK_LSE above this defaults to 0 because LSE is
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* mandatory for MSI/LSE-trimming to work */
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#define CLOCK_MSI_LSE_PLL (0)
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#endif
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/* give the target core clock (HCLK) frequency [in Hz], maximum: 80MHz */
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#define CLOCK_CORECLOCK (80000000U)
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/* PLL configuration: make sure your values are legit!
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@ -36,6 +36,12 @@ extern "C" {
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/* 0: no external low speed crystal available,
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* 1: external crystal available (always 32.768kHz) */
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#define CLOCK_LSE (1)
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/* 0: enable MSI only if HSE isn't available
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* 1: always enable MSI (e.g. if USB or RNG is used)*/
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#define CLOCK_MSI_ENABLE (1)
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/* 0: disable Hardware auto calibration with LSE
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* 1: enable Hardware auto calibration with LSE (PLL-mode)*/
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#define CLOCK_MSI_LSE_PLL (1)
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/* give the target core clock (HCLK) frequency [in Hz], maximum: 80MHz */
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#define CLOCK_CORECLOCK (80000000U)
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/* PLL configuration: make sure your values are legit!
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@ -1,5 +1,6 @@
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/*
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* Copyright (C) 2017 Freie Universität Berlin
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* 2017 HAW-Hamburg
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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@ -15,150 +16,15 @@
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*
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* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
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* @author Nick van IJzendoorn <nijzendoorn@engineering-spirit.nl>
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* @author Michel Rottleuthner <michel.rottleuthner@haw-hamburg.de>
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* @}
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*/
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#include <stdint.h>
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#include "cpu.h"
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#include "irq.h"
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#include "stmclk.h"
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#include "periph_conf.h"
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#include "periph/init.h"
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/* make sure we have all needed information about the clock configuration */
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#ifndef CLOCK_HSE
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#error "Please provide CLOCK_HSE in your board's perhip_conf.h"
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#endif
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#ifndef CLOCK_LSE
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#error "Please provide CLOCK_LSE in your board's periph_conf.h"
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#endif
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#if !defined(CLOCK_PLL_M) || !defined(CLOCK_PLL_N) || !defined(CLOCK_PLL_R)
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#error "Please provide the PLL configuration in your board's periph_conf.h"
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#endif
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/**
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* @name PLL configuration
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* @{
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*/
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/* figure out which input to use */
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#if (CLOCK_HSE)
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#define PLL_IN CLOCK_HSE
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#define PLL_SRC RCC_PLLCFGR_PLLSRC_HSE
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#else
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#define PLL_IN (48000000) /* MSI @ 48MHz */
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#define PLL_SRC RCC_PLLCFGR_PLLSRC_MSI
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#endif
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/**check configuration and get the corresponding bitfields */
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#if (CLOCK_PLL_M < 1 || CLOCK_PLL_M > 8)
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#error "PLL configuration: PLL M value is out of range"
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#endif
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#define PLL_M ((CLOCK_PLL_M - 1) << RCC_PLLCFGR_PLLM_Pos)
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#if (CLOCK_PLL_N < 8 || CLOCK_PLL_N > 86)
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#error "PLL configuration: PLL N value is out of range"
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#endif
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#define PLL_N (CLOCK_PLL_N << RCC_PLLCFGR_PLLN_Pos)
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#if (CLOCK_PLL_R == 2)
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#define PLL_R (0)
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#elif (CLOCK_PLL_R == 4)
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#define PLL_R (RCC_PLLCFGR_PLLR_0)
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#elif (CLOCK_PLL_R == 6)
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#define PLL_R (RCC_PLLCFGR_PLLR_1)
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#elif (CLOCK_PLL_R == 8)
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#define PLL_R (RCC_PLLCFGR_PLLR_0 | RCC_PLLCFGR_PLLR_1)
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#else
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#error "PLL configuration: PLL R value is invalid"
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#endif
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/** @} */
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/**
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* @name Deduct the needed flash wait states from the core clock frequency
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* @{
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*/
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#if (CLOCK_CORECLOCK <= 16000000)
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#define FLASH_WAITSTATES FLASH_ACR_LATENCY_0WS
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#elif (CLOCK_CORECLOCK <= 32000000)
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#define FLASH_WAITSTATES FLASH_ACR_LATENCY_1WS
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#elif (CLOCK_CORECLOCK <= 48000000)
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#define FLASH_WAITSTATES FLASH_ACR_LATENCY_2WS
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#elif (CLOCK_CORECLOCK <= 64000000)
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#define FLASH_WAITSTATES FLASH_ACR_LATENCY_3WS
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#else
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#define FLASH_WAITSTATES FLASH_ACR_LATENCY_4WS
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#endif
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/** @} */
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/**
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* @brief Configure the STM32L4's clock system
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*
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* We use the following configuration:
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* - we always enable the 32kHz low speed clock (LSI or LSE)
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* - we configure the MSI clock to 48MHz (for USB and RNG) and enable it
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* - if LSE present, we use it to stabilize the 48MHz MSI clock (MSIPLLEN)
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* - use either MSI @ 48MHz or HSE (4 to 48MHZ) as base clock
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* - we use the PLL as main clock provider
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* - we don't enable any ASI clock
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*
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* For the computation of the PLL configuration, see defines above.
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*/
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static void cpu_clock_init(void)
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{
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/* disable any interrupts. Global interrupts could be enabled if this is
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* called from some kind of bootloader... */
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unsigned is = irq_disable();
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RCC->CIER = 0;
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/* for the duration of the configuration, we fall-back to the maximum number
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* of flash wait states */
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FLASH->ACR = (FLASH_ACR_LATENCY_4WS);
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/* reset clock to MSI with 48MHz, disables all other clocks */
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RCC->CR = (RCC_CR_MSIRANGE_11 | RCC_CR_MSION | RCC_CR_MSIRGSEL);
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while (!(RCC->CR & RCC_CR_MSIRDY)) {}
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/* use MSI as system clock while we do any further configuration and
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* configure the AHB and APB clock dividers as configure by the board */
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RCC->CFGR = (RCC_CFGR_SW_MSI | CLOCK_AHB_DIV |
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CLOCK_APB1_DIV | CLOCK_APB2_DIV);
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while ((RCC->CFGR & RCC_CFGR_SWS_Msk) != RCC_CFGR_SWS_MSI) {}
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/* configure the low speed clock domain (LSE vs LSI) */
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#if CLOCK_LSE
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/* we enable the LSE clock if available for calibrating the MSI clock */
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stmclk_enable_lfclk();
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/* now we can enable the MSI PLL mode */
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RCC->CR |= RCC_CR_MSIPLLEN;
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while (!(RCC->CR & RCC_CR_MSIRDY)) {}
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#endif
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/* select the MSI clock for the 48MHz clock tree (USB, RNG) */
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RCC->CCIPR = (RCC_CCIPR_CLK48SEL_0 | RCC_CCIPR_CLK48SEL_1);
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/* if configured: enable the HSE clock */
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#if CLOCK_HSE
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RCC->CR |= RCC_CR_HSEON;
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while (!(RCC->CR & RCC_CR_HSERDY)) {}
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#endif
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/* next we configure and enable the PLL */
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RCC->PLLCFGR = (PLL_SRC | PLL_M | PLL_N | PLL_R | RCC_PLLCFGR_PLLREN);
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RCC->CR |= RCC_CR_PLLON;
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while (!(RCC->CR & RCC_CR_PLLRDY)) {}
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/* now tell the system to use the PLL as main clock */
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RCC->CFGR |= RCC_CFGR_SW_PLL;
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while ((RCC->CFGR & RCC_CFGR_SWS_Msk) != RCC_CFGR_SWS_PLL) {}
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/* finally we enable I+D cashes, pre-fetch, and we set the actual number of
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* needed flash wait states */
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FLASH->ACR = (FLASH_ACR_ICEN | FLASH_ACR_DCEN |
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FLASH_ACR_PRFTEN | FLASH_WAITSTATES);
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irq_restore(is);
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}
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/**
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* @brief Initialize the CPU, set IRQ priorities
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*/
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@ -167,7 +33,7 @@ void cpu_init(void)
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/* initialize the Cortex-M core */
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cortexm_init();
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/* initialize the clock system */
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cpu_clock_init();
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stmclk_init_sysclk();
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/* trigger static peripheral initialization */
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periph_init();
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}
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160
cpu/stm32l4/stmclk.c
Normal file
160
cpu/stm32l4/stmclk.c
Normal file
@ -0,0 +1,160 @@
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/*
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* Copyright (C) 2017 Freie Universität Berlin
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* 2017 OTA keys S.A.
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* 2017 HAW-Hamburg
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup cpu_stm32l4
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* @{
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*
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* @file
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* @brief Implementation of STM32 clock configuration
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*
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* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
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* @author Nick van IJzendoorn <nijzendoorn@engineering-spirit.nl>
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* @author Vincent Dupont <vincent@otakeys.com>
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* @author Michel Rottleuthner <michel.rottleuthner@haw-hamburg.de>
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* @}
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*/
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#include "cpu.h"
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#include "stmclk.h"
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#include "periph_conf.h"
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/* make sure we have all needed information about the clock configuration */
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#ifndef CLOCK_HSE
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#error "Please provide CLOCK_HSE in your board's perhip_conf.h"
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#endif
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#ifndef CLOCK_LSE
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#error "Please provide CLOCK_LSE in your board's periph_conf.h"
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#endif
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#if !defined(CLOCK_PLL_M) || !defined(CLOCK_PLL_N) || !defined(CLOCK_PLL_R)
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#error "Please provide the PLL configuration in your board's periph_conf.h"
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#endif
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/**
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* @name PLL configuration
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* @{
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*/
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/* figure out which input to use */
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#if (CLOCK_HSE)
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#define PLL_IN CLOCK_HSE
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#define PLL_SRC RCC_PLLCFGR_PLLSRC_HSE
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#else
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#define PLL_IN (48000000) /* MSI @ 48MHz */
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#define PLL_SRC RCC_PLLCFGR_PLLSRC_MSI
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#endif
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/**check configuration and get the corresponding bitfields */
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#if (CLOCK_PLL_M < 1 || CLOCK_PLL_M > 8)
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#error "PLL configuration: PLL M value is out of range"
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#endif
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#define PLL_M ((CLOCK_PLL_M - 1) << RCC_PLLCFGR_PLLM_Pos)
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#if (CLOCK_PLL_N < 8 || CLOCK_PLL_N > 86)
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#error "PLL configuration: PLL N value is out of range"
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#endif
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#define PLL_N (CLOCK_PLL_N << RCC_PLLCFGR_PLLN_Pos)
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#if (CLOCK_PLL_R == 2)
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#define PLL_R (0)
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#elif (CLOCK_PLL_R == 4)
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#define PLL_R (RCC_PLLCFGR_PLLR_0)
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#elif (CLOCK_PLL_R == 6)
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#define PLL_R (RCC_PLLCFGR_PLLR_1)
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#elif (CLOCK_PLL_R == 8)
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#define PLL_R (RCC_PLLCFGR_PLLR_0 | RCC_PLLCFGR_PLLR_1)
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#else
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#error "PLL configuration: PLL R value is invalid"
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#endif
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/** @} */
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/**
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* @name Deduct the needed flash wait states from the core clock frequency
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* @{
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*/
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#if (CLOCK_CORECLOCK <= 16000000)
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#define FLASH_WAITSTATES FLASH_ACR_LATENCY_0WS
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#elif (CLOCK_CORECLOCK <= 32000000)
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#define FLASH_WAITSTATES FLASH_ACR_LATENCY_1WS
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#elif (CLOCK_CORECLOCK <= 48000000)
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#define FLASH_WAITSTATES FLASH_ACR_LATENCY_2WS
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#elif (CLOCK_CORECLOCK <= 64000000)
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#define FLASH_WAITSTATES FLASH_ACR_LATENCY_3WS
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#else
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#define FLASH_WAITSTATES FLASH_ACR_LATENCY_4WS
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#endif
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/** @} */
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void stmclk_init_sysclk(void)
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{
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/* disable any interrupts. Global interrupts could be enabled if this is
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* called from some kind of bootloader... */
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unsigned is = irq_disable();
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RCC->CIER = 0;
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/* enable HSI clock for the duration of initialization */
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stmclk_enable_hsi();
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/* use HSI as system clock while we do any further configuration and
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* configure the AHB and APB clock dividers as configure by the board */
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RCC->CFGR = (RCC_CFGR_SW_HSI | CLOCK_AHB_DIV |
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CLOCK_APB1_DIV | CLOCK_APB2_DIV);
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while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI) {}
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/* we enable I+D cashes, pre-fetch, and we set the actual number of
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* needed flash wait states */
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FLASH->ACR = (FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_PRFTEN |
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FLASH_WAITSTATES);
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/* disable all active clocks except HSI -> resets the clk configuration
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* Note: on STM32L4x5 & STM32L4x6 this disables the following:
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PLLSAI2, PLLSAI1, Main PLL (via PLLON),
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Clock security system (via CSSON), MSI clock PLL (via MSIPLLEN),
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HSE crystal oscillator bypass (via HSEBYP), HSE,
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HSI16 automatic start from Stop (via HSIASFS),
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HSI16 always enable for peripheral kernels (via HSIKERON).
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Additionally it configures the MSI clock range (MSIRANGE) to
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~100 kHz and the MSI clock to be based on MSISRANGE in RCC_CSR
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(instead of MSIRANGE in the RCC_CR) */
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RCC->CR = (RCC_CR_HSION);
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#if (CLOCK_HSE)
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/* if configured, we need to enable the HSE clock now */
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RCC->CR |= (RCC_CR_HSEON);
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while (!(RCC->CR & RCC_CR_HSERDY)) {}
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#endif
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#if ((CLOCK_HSE == 0) || CLOCK_MSI_ENABLE)
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/* reset clock to MSI with 48MHz, disables all other clocks */
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RCC->CR = (RCC_CR_MSIRANGE_11 | RCC_CR_MSION | RCC_CR_MSIRGSEL);
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while (!(RCC->CR & RCC_CR_MSIRDY)) {}
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/* select the MSI clock for the 48MHz clock tree (USB, RNG) */
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RCC->CCIPR = (RCC_CCIPR_CLK48SEL_0 | RCC_CCIPR_CLK48SEL_1);
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#if (CLOCK_MSI_LSE_PLL && CLOCK_LSE)
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/* configure the low speed clock domain */
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stmclk_enable_lfclk();
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/* now we can enable the MSI PLL mode to enhance accuracy of the MSI*/
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RCC->CR |= RCC_CR_MSIPLLEN;
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while (!(RCC->CR & RCC_CR_MSIRDY)) {}
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#endif /* (CLOCK_MSI_LSE_PLL && CLOCK_LSE) */
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#endif /* ((CLOCK_HSE == 0) || CLOCK_MSI_ENABLE) */
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/* now we can safely configure and start the PLL */
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RCC->PLLCFGR = (PLL_SRC | PLL_M | PLL_N | PLL_R | RCC_PLLCFGR_PLLREN);
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RCC->CR |= (RCC_CR_PLLON);
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while (!(RCC->CR & RCC_CR_PLLRDY)) {}
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/* now that the PLL is running, we use it as system clock */
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RCC->CFGR |= (RCC_CFGR_SW_PLL);
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while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_PLL) {}
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stmclk_disable_hsi();
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irq_restore(is);
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}
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