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boards/sipeed-longan-nano: improve ADC config
The ADC configuration was too complex. It was hard to follow when certain ADC lines are available. Furthermore, the order of ADC lines did depend on the use of other peripherals. Now, either the TFT display is not connected and all ADC lines are available or the TFT display is connected and the second SPI device is used so that only the first 4 ADC lines are available.
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@ -33,6 +33,10 @@
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#define CONFIG_CLOCK_HXTAL MHZ(8) /**< HXTAL frequency */
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#endif
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#if CONFIG_SIPEED_LONGAN_NANO_WITH_TFT
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#define SPI_DEV_1_USED /**< Enable SPI_DEV(1) if TFT is connected */
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#endif
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#include "periph_cpu.h"
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#include "periph_common_conf.h"
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@ -56,22 +60,18 @@ static const adc_conf_t adc_config[] = {
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{ .pin = GPIO_UNDEF, .dev = 0, .chan = 16 },
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/* ADC VREF channel */
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{ .pin = GPIO_UNDEF, .dev = 0, .chan = 17 },
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#if !defined(CONFIG_SIPEED_LONGAN_NANO_WITH_TFT)
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#if !CONFIG_SIPEED_LONGAN_NANO_WITH_TFT
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/* This conflicts with TFT pins if connected. */
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{ .pin = GPIO_PIN(PORT_B, 0), .dev = 0, .chan = 8 },
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{ .pin = GPIO_PIN(PORT_B, 1), .dev = 0, .chan = 9 },
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#endif
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#if !defined(MODULE_PERIPH_SPI)
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/* This conflicts with the SPI0 controller which is used for TFT if connected */
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{ .pin = GPIO_PIN(PORT_A, 4), .dev = 0, .chan = 4 },
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#if !defined(CONFIG_SIPEED_LONGAN_NANO_WITH_TFT)
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{ .pin = GPIO_PIN(PORT_A, 5), .dev = 0, .chan = 5 },
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#endif /* !defined(CONFIG_SIPEED_LONGAN_NANO_WITH_TFT) */
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/* This conflicts with the SPI0 controller which is used is TFT is connected */
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{ .pin = GPIO_PIN(PORT_A, 6), .dev = 0, .chan = 6 },
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#if !defined(CONFIG_SIPEED_LONGAN_NANO_WITH_TFT)
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{ .pin = GPIO_PIN(PORT_A, 7), .dev = 0, .chan = 7 },
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#endif /* !defined(CONFIG_SIPEED_LONGAN_NANO_WITH_TFT) */
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#endif
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#if !defined(MODULE_PERIPH_DAC)
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{ .pin = GPIO_PIN(PORT_A, 4), .dev = 0, .chan = 4 },
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{ .pin = GPIO_PIN(PORT_A, 5), .dev = 0, .chan = 5 },
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#endif /* !defined(MODULE_PERIPH_DAC) */
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#endif /* !CONFIG_SIPEED_LONGAN_NANO_WITH_TFT */
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};
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#define ADC_NUMOF ARRAY_SIZE(adc_config)
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