mirror of
https://github.com/RIOT-OS/RIOT.git
synced 2024-12-29 04:50:03 +01:00
cpu/stm32f1: reworked clock initialization code
This commit is contained in:
Hauke Petersen
parent
4b9935b4f2
commit
c866634469
@ -29,19 +29,34 @@ extern "C" {
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* @name Clock system configuration
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* @{
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**/
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#define CLOCK_HSE (16000000U) /* frequency of external oscillator */
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#define CLOCK_CORECLOCK (72000000U) /* targeted core clock frequency */
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/* configuration of PLL prescaler and multiply values */
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/* CORECLOCK := CLOCK_SOURCE / PLL_DIV * PLL_MUL */
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/* high speed clock configuration:
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* 0 := use internal HSI oscillator (always 8MHz)
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* HSE frequency value := use external HSE oscillator with given freq [in Hz]
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* must be 4000000 <= value <= 16000000 */
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#define CLOCK_HSE (16000000U)
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/* low speed clock configuration:
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* 0 := use internal LSI oscillator (~40kHz)
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* 1 := use extern LSE oscillator, always 32.768kHz */
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#define CLOCK_LSE (1)
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/* targeted system clock speed [in Hz], must be <= 72MHz */
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#define CLOCK_CORECLOCK (72000000U)
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/* PLL configuration, set both values to zero to disable PLL usage. The values
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* must be set to satisfy the following equation:
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* CORECLOCK := CLOCK_SOURCE / PLL_DIV * PLL_MUL
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* with
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* 1 <= CLOCK_PLL_DIV <= 2
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* 2 <= CLOCK_PLL_MUL <= 17 */
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#define CLOCK_PLL_DIV (2)
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#define CLOCK_PLL_MUL (9)
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/* configuration of peripheral bus clock prescalers */
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#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1 /* AHB clock -> 72MHz */
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#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* APB2 clock -> 72MHz */
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#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2 /* APB1 clock -> 36MHz */
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/* resulting bus clocks */
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/* AHB and APBx bus clock configuration, keep in mind the following constraints:
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* ABP1 <= 36MHz
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*/
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#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
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#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
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#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1
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#define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
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#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2
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#define CLOCK_APB1 (CLOCK_CORECLOCK / 2)
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#define CLOCK_APB2 (CLOCK_CORECLOCK)
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/** @} */
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/**
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@ -30,20 +30,33 @@ extern "C" {
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* @name Clock system configuration
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* @{
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**/
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#define CLOCK_HSE (16000000U) /* frequency of external oscillator */
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#define CLOCK_CORECLOCK (72000000U) /* targeted core clock frequency */
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/* configuration of PLL prescaler and multiply values */
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/* CORECLOCK := CLOCK_SOURCE / PLL_DIV * PLL_MUL */
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/* high speed clock configuration:
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* 0 := use internal HSI oscillator (always 8MHz)
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* HSE frequency value := use external HSE oscillator with given freq [in Hz]
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* must be 4000000 <= value <= 16000000 */
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#define CLOCK_HSE (16000000U)
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/* low speed clock configuration:
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* 0 := use internal LSI oscillator (~40kHz)
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* 1 := use extern LSE oscillator, always 32.768kHz */
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#define CLOCK_LSE (1)
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/* targeted system clock speed [in Hz], must be <= 72MHz */
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#define CLOCK_CORECLOCK (72000000U)
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/* PLL configuration, set both values to zero to disable PLL usage. The values
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* must be set to satisfy the following equation:
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* CORECLOCK := CLOCK_SOURCE / PLL_DIV * PLL_MUL
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* with
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* 1 <= CLOCK_PLL_DIV <= 2
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* 2 <= CLOCK_PLL_MUL <= 17 */
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#define CLOCK_PLL_DIV (2)
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#define CLOCK_PLL_MUL (9)
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/* configuration of peripheral bus clock prescalers */
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#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1 /* AHB clock -> 72MHz */
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#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* APB2 clock -> 72MHz */
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#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2 /* APB1 clock -> 36MHz */
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/* bus clocks for simplified peripheral initialization, UPDATE MANUALLY! */
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/* AHB and APBx bus clock configuration, keep in mind the following constraints:
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* ABP1 <= 36MHz
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*/
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#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
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#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
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#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1
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#define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
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#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2
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#define CLOCK_APB1 (CLOCK_CORECLOCK / 2)
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/** @} */
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@ -26,27 +26,37 @@ extern "C" {
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#endif
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/**
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* @name Clock system configuration
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* @name Clock system configuration
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* @{
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*/
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#define CLOCK_HSE (8000000U) /* external oscillator */
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#define CLOCK_CORECLOCK (72000000U) /* desired core clock frequency */
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/* the actual PLL values are automatically generated */
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**/
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/* high speed clock configuration:
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* 0 := use internal HSI oscillator (always 8MHz)
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* HSE frequency value := use external HSE oscillator with given freq [in Hz]
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* must be 4000000 <= value <= 16000000 */
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#define CLOCK_HSE (8000000U)
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/* low speed clock configuration:
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* 0 := use internal LSI oscillator (~40kHz)
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* 1 := use extern LSE oscillator, always 32.768kHz */
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#define CLOCK_LSE (0)
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/* targeted system clock speed [in Hz], must be <= 72MHz */
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#define CLOCK_CORECLOCK (72000000U)
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/* PLL configuration, set both values to zero to disable PLL usage. The values
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* must be set to satisfy the following equation:
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* CORECLOCK := CLOCK_SOURCE / PLL_DIV * PLL_MUL
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* with
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* 1 <= CLOCK_PLL_DIV <= 2
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* 2 <= CLOCK_PLL_MUL <= 17 */
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#define CLOCK_PLL_DIV (1)
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#define CLOCK_PLL_MUL CLOCK_CORECLOCK / CLOCK_HSE
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/* AHB, APB1, APB2 dividers */
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#define CLOCK_PLL_MUL (9)
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/* AHB and APBx bus clock configuration, keep in mind the following constraints:
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* ABP1 <= 36MHz
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*/
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#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
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#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
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#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1
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#define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
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#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2
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/* Bus clocks */
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#define CLOCK_APB1 (CLOCK_CORECLOCK / 2)
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#define CLOCK_APB2 (CLOCK_CORECLOCK)
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/* Flash latency */
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#define CLOCK_FLASH_LATENCY FLASH_ACR_LATENCY_2 /* for >= 72 MHz */
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/** @} */
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/**
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@ -26,22 +26,36 @@ extern "C" {
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#endif
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/**
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* @name Clock system configuration
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* @name Clock system configuration
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* @{
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*/
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#define CLOCK_HSE (8000000U) /* external oscillator */
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#define CLOCK_CORECLOCK (72000000U) /* desired core clock frequency */
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/* the actual PLL values are automatically generated */
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**/
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/* high speed clock configuration:
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* 0 := use internal HSI oscillator (always 8MHz)
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* HSE frequency value := use external HSE oscillator with given freq [in Hz]
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* must be 4000000 <= value <= 16000000 */
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#define CLOCK_HSE (8000000U)
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/* low speed clock configuration:
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* 0 := use internal LSI oscillator (~40kHz)
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* 1 := use extern LSE oscillator, always 32.768kHz */
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#define CLOCK_LSE (1)
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/* targeted system clock speed [in Hz], must be <= 72MHz */
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#define CLOCK_CORECLOCK (72000000U)
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/* PLL configuration, set both values to zero to disable PLL usage. The values
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* must be set to satisfy the following equation:
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* CORECLOCK := CLOCK_SOURCE / PLL_DIV * PLL_MUL
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* with
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* 1 <= CLOCK_PLL_DIV <= 2
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* 2 <= CLOCK_PLL_MUL <= 17 */
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#define CLOCK_PLL_DIV (1)
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#define CLOCK_PLL_MUL (9)
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/* AHB, APB1, APB2 dividers */
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/* AHB and APBx bus clock configuration, keep in mind the following constraints:
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* ABP1 <= 36MHz
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*/
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#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
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#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1
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#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2 /* max 36 MHz (!) */
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/* bus clocks for simplified peripheral initialization, UPDATE MANUALLY! */
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#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
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#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1
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#define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
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#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2
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#define CLOCK_APB1 (CLOCK_CORECLOCK / 2)
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/** @} */
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@ -26,27 +26,37 @@ extern "C" {
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#endif
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/**
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* @name Clock system configuration
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* @name Clock system configuration
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* @{
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*/
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#define CLOCK_HSE (8000000U) /* external oscillator */
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#define CLOCK_CORECLOCK (72000000U) /* desired core clock frequency */
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/* the actual PLL values are automatically generated */
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**/
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/* high speed clock configuration:
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* 0 := use internal HSI oscillator (always 8MHz)
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* HSE frequency value := use external HSE oscillator with given freq [in Hz]
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* must be 4000000 <= value <= 16000000 */
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#define CLOCK_HSE (8000000U)
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/* low speed clock configuration:
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* 0 := use internal LSI oscillator (~40kHz)
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* 1 := use extern LSE oscillator, always 32.768kHz */
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#define CLOCK_LSE (0)
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/* targeted system clock speed [in Hz], must be <= 72MHz */
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#define CLOCK_CORECLOCK (72000000U)
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/* PLL configuration, set both values to zero to disable PLL usage. The values
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* must be set to satisfy the following equation:
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* CORECLOCK := CLOCK_SOURCE / PLL_DIV * PLL_MUL
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* with
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* 1 <= CLOCK_PLL_DIV <= 2
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* 2 <= CLOCK_PLL_MUL <= 17 */
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#define CLOCK_PLL_DIV (1)
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#define CLOCK_PLL_MUL CLOCK_CORECLOCK / CLOCK_HSE
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/* AHB, APB1, APB2 dividers */
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#define CLOCK_PLL_MUL (9)
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/* AHB and APBx bus clock configuration, keep in mind the following constraints:
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* ABP1 <= 36MHz
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*/
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#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
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#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
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#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1
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#define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
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#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2
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/* Bus clocks */
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#define CLOCK_APB1 (CLOCK_CORECLOCK / 2)
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#define CLOCK_APB2 (CLOCK_CORECLOCK)
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/* Flash latency */
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#define CLOCK_FLASH_LATENCY FLASH_ACR_LATENCY_2 /* for >= 72 MHz */
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/** @} */
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/**
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@ -26,22 +26,37 @@
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#endif
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/**
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* @name Clock system configuration
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* @name Clock system configuration
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* @{
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**/
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#define CLOCK_HSE (8000000U) /* frequency of external oscillator */
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#define CLOCK_CORECLOCK (72000000U) /* targeted core clock frequency */
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/* configuration of PLL prescaler and multiply values */
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/* CORECLOCK := HSE / PLL_HSE_DIV * PLL_HSE_MUL */
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/* high speed clock configuration:
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* 0 := use internal HSI oscillator (always 8MHz)
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* HSE frequency value := use external HSE oscillator with given freq [in Hz]
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* must be 4000000 <= value <= 16000000 */
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#define CLOCK_HSE (8000000U)
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/* low speed clock configuration:
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* 0 := use internal LSI oscillator (~40kHz)
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* 1 := use extern LSE oscillator, always 32.768kHz */
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#define CLOCK_LSE (0)
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/* targeted system clock speed [in Hz], must be <= 72MHz */
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#define CLOCK_CORECLOCK (72000000U)
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/* PLL configuration, set both values to zero to disable PLL usage. The values
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* must be set to satisfy the following equation:
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* CORECLOCK := CLOCK_SOURCE / PLL_DIV * PLL_MUL
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* with
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* 1 <= CLOCK_PLL_DIV <= 2
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* 2 <= CLOCK_PLL_MUL <= 17 */
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#define CLOCK_PLL_DIV (1)
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#define CLOCK_PLL_MUL (9)
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/* configuration of peripheral bus clock prescalers */
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#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1 /* AHB clock -> 72MHz */
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#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* APB2 clock -> 72MHz */
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#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2 /* APB1 clock -> 36MHz */
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/* resulting bus clocks */
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/* AHB and APBx bus clock configuration, keep in mind the following constraints:
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* ABP1 <= 36MHz
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*/
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#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
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#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
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#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1
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#define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
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#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2
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#define CLOCK_APB1 (CLOCK_CORECLOCK / 2)
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#define CLOCK_APB2 (CLOCK_CORECLOCK)
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/** @} */
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/**
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@ -26,139 +26,15 @@
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*/
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#include "cpu.h"
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#include "periph_conf.h"
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#include "stmclk.h"
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#include "periph/init.h"
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/* Configuration of flash access cycles */
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#if CLOCK_CORECLOCK <= 24000000
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#define FLASH_LATENCY (0) /* Zero wait state, if 0 < SYSCLK≤ 24 MHz */
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#elif CLOCK_CORECLOCK <= 48000000
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#define FLASH_LATENCY (1) /* One wait states, if 24 MHz < SYSCLK ≤ 48 MHz */
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#elif CLOCK_CORECLOCK <= 72000000
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#define FLASH_LATENCY (2) /* Two wait states, if 48 MHz < SYSCLK ≤ 72 MHz */
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#endif
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/* See if we want to use the PLL */
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#if defined(CLOCK_PLL_DIV) || defined(CLOCK_PLL_MUL)
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#define CLOCK_USE_PLL 1
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#else
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#define CLOCK_USE_PLL 0
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#endif
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/* Check the source to be used and parameters */
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#if defined(CLOCK_HSI) && defined(CLOCK_HSE)
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#error "Only provide one of two CLOCK_HSI/CLOCK_HSE"
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#elif (CLOCK_USE_PLL == 1) && (!defined(CLOCK_PLL_MUL) || !defined(CLOCK_PLL_DIV))
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#error "When using PLL both CLOCK_PLL_DIV and CLOCK_PLL_MUL must be provided"
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#elif CLOCK_HSI
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#define CLOCK_CR_SOURCE RCC_CR_HSION
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#define CLOCK_CR_SOURCE_RDY RCC_CR_HSIRDY
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#define CLOCK_PLL_DIVMSK 0
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#define CLOCK_PLL_SOURCE 0
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#define CLOCK_DISABLE_HSI 0
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#if (CLOCK_USE_PLL == 0)
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#define CLOCK_CFGR_SW RCC_CFGR_SW_HSI
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#define CLOCK_CFGR_SW_RDY RCC_CFGR_SWS_HSI
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#elif (CLOCK_PLL_DIV != 2)
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#error "CLOCK_PLL_DIV can only be 2 for the HSI"
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#endif
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#elif CLOCK_HSE
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#define CLOCK_CR_SOURCE RCC_CR_HSEON
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#define CLOCK_CR_SOURCE_RDY RCC_CR_HSERDY
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#define CLOCK_PLL_SOURCE RCC_CFGR_PLLSRC
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#define CLOCK_DISABLE_HSI 1
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#if (CLOCK_USE_PLL == 0)
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#define CLOCK_CFGR_SW RCC_CFGR_SW_HSE
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#define CLOCK_CFGR_SW_RDY RCC_CFGR_SWS_HSE
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#elif (CLOCK_PLL_DIV == 2)
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#define CLOCK_PLL_DIVMSK RCC_CFGR_PLLXTPRE
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#elif (CLOCK_PLL_DIV == 1)
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#define CLOCK_PLL_DIVMSK 0
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#elif defined(CLOCK_PLL_DIV)
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#error "HSE divider must be 1 or 2"
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#endif
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#else
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#error "Please provide CLOCK_HSI or CLOCK_HSE in boards/NAME/includes/perhip_cpu.h"
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#endif
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#if (CLOCK_USE_PLL == 1)
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#define CLOCK_CFGR_SW RCC_CFGR_SW_PLL
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#define CLOCK_CFGR_SW_RDY RCC_CFGR_SWS_PLL
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#if CLOCK_PLL_MUL > 16
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#error "PLL multiplier cannot exceed 16 times"
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#elif CLOCK_PLL_MUL < 2
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#error "PLL multiplier cannot be set to 1 or lower"
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#endif
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#endif
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static void clk_init(void);
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void cpu_init(void)
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{
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/* initialize the Cortex-M core */
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cortexm_init();
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/* initialize system clocks */
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clk_init();
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/* initialize the system clock as configured in the periph_conf.h */
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stmclk_init_sysclk();
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/* trigger static peripheral initialization */
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periph_init();
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}
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/**
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* @brief Configure the clock system of the stm32f1
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*/
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static void clk_init(void)
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{
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/* Reset the RCC clock configuration to the default reset state(for debug purpose) */
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/* Set HSION bit */
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RCC->CR |= (uint32_t)0x00000001;
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/* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
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RCC->CFGR &= (uint32_t)0xF0FF0000;
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/* Reset HSEON, CSSON and PLLON bits */
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RCC->CR &= (uint32_t)0xFEF6FFFF;
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/* Reset HSEBYP bit */
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RCC->CR &= (uint32_t)0xFFFBFFFF;
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/* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
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RCC->CFGR &= (uint32_t)0xFF80FFFF;
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/* Disable all interrupts and clear pending bits */
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RCC->CIR = (uint32_t)0x009F0000;
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/* SYSCLK, HCLK, PCLK2 and PCLK1 configuration */
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/* Enable high speed clock source */
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RCC->CR |= ((uint32_t)CLOCK_CR_SOURCE);
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/* Wait till the high speed clock source is ready
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* NOTE: the MCU will stay here forever if you use an external clock source and it's not connected */
|
||||
while ((RCC->CR & CLOCK_CR_SOURCE_RDY) == 0) {}
|
||||
/* Enable prefetch buffer and set flash wait state */
|
||||
FLASH->ACR = (uint32_t)(FLASH_ACR_PRFTBE | FLASH_LATENCY);
|
||||
/* HCLK = SYSCLK */
|
||||
RCC->CFGR |= (uint32_t)CLOCK_AHB_DIV;
|
||||
/* PCLK2 = HCLK */
|
||||
RCC->CFGR |= (uint32_t)CLOCK_APB2_DIV;
|
||||
/* PCLK1 = HCLK */
|
||||
RCC->CFGR |= (uint32_t)CLOCK_APB1_DIV;
|
||||
|
||||
#if (CLOCK_USE_PLL == 1)
|
||||
/* PLL configuration: PLLCLK = CLOCK_SOURCE / PLL_DIV * PLL_MUL */
|
||||
RCC->CFGR |= (uint32_t)(CLOCK_PLL_SOURCE | CLOCK_PLL_DIVMSK | ((CLOCK_PLL_MUL - 2) << 18));
|
||||
/* Enable PLL */
|
||||
RCC->CR |= RCC_CR_PLLON;
|
||||
/* Wait till PLL is ready */
|
||||
while ((RCC->CR & RCC_CR_PLLRDY) == 0) {}
|
||||
#endif
|
||||
|
||||
/* Select the system clock source */
|
||||
RCC->CFGR &= ~((uint32_t)(RCC_CFGR_SW));
|
||||
RCC->CFGR |= (uint32_t)CLOCK_CFGR_SW;
|
||||
/* Wait till selected system clock source is ready */
|
||||
while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != CLOCK_CFGR_SW_RDY) {}
|
||||
|
||||
#if CLOCK_DISABLE_HSI
|
||||
RCC->CR &= ~(RCC_CR_HSION);
|
||||
while ((RCC->CR & RCC_CR_HSIRDY) != 0) {}
|
||||
#endif
|
||||
}
|
||||
|
||||
209
cpu/stm32f1/stmclk.c
Normal file
209
cpu/stm32f1/stmclk.c
Normal file
@ -0,0 +1,209 @@
|
||||
/*
|
||||
* Copyright (C) 2017 Freie Universität Berlin
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU Lesser
|
||||
* General Public License v2.1. See the file LICENSE in the top level
|
||||
* directory for more details.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @ingroup cpu_stm32f1
|
||||
* @{
|
||||
*
|
||||
* @file
|
||||
* @brief Implementation of STM32F1 clock configuration
|
||||
*
|
||||
* @author Stefan Pfeiffer <stefan.pfeiffer@fu-berlin.de>
|
||||
* @author Alaeddine Weslati <alaeddine.weslati@inria.fr>
|
||||
* @author Thomas Eichinger <thomas.eichinger@fu-berlin.de>
|
||||
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
|
||||
* @author Nick van IJzendoorn <nijzendoorn@engineering-spirit.nl>
|
||||
* @author Víctor Ariño <victor.arino@zii.aero>
|
||||
*
|
||||
* @}
|
||||
*/
|
||||
|
||||
#include "irq.h"
|
||||
#include "cpu.h"
|
||||
#include "stmclk.h"
|
||||
#include "periph_conf.h"
|
||||
|
||||
/* make sure we have all needed information about the clock configuration */
|
||||
#ifndef CLOCK_HSE
|
||||
#error "Please provide CLOCK_HSE in your board's perhip_conf.h"
|
||||
#endif
|
||||
#ifndef CLOCK_LSE
|
||||
#error "Please provide CLOCK_LSE in your board's periph_conf.h"
|
||||
#endif
|
||||
#ifndef CLOCK_CORECLOCK
|
||||
#error "Please provide CLOCK_CORECLOCK in your board's periph_conf.h"
|
||||
#endif
|
||||
#if !defined(CLOCK_PLL_MUL) || !defined(CLOCK_PLL_DIV)
|
||||
#error "Please provide a valid PLL configuration in your board's periph_conf.h"
|
||||
#endif
|
||||
#if !defined(CLOCK_AHB_DIV) || !defined(CLOCK_AHB) || \
|
||||
!defined(CLOCK_APB1_DIV) || !defined(CLOCK_APB1) || \
|
||||
!defined(CLOCK_APB2_DIV) || !defined(CLOCK_APB2)
|
||||
#error "Please provide a AHB and APBx configuration in your board configuration"
|
||||
#endif
|
||||
|
||||
/* make sure the selected system clock is valid */
|
||||
#if (CLOCK_CORECLOCK > 72000000)
|
||||
#error "clock config: the selected system clock exceeds 72MHz"
|
||||
#endif
|
||||
|
||||
/* figure out which base block to use */
|
||||
#if CLOCK_HSE
|
||||
#if (CLOCK_HSE < 4000000) || (CLOCK_HSE > 16000000)
|
||||
#error "clock config: HSE value is out of valid range"
|
||||
#endif
|
||||
#define BASECLK (CLOCK_HSE)
|
||||
#else
|
||||
#define BASECLK (8000000) /* HSI is alway 8MHz */
|
||||
#endif
|
||||
|
||||
/* if PLL is configured, verify its parameters */
|
||||
#if (CLOCK_PLL_DIV && CLOCK_PLL_MUL)
|
||||
#define USEPLL
|
||||
/* check clock config */
|
||||
#if (CLOCK_CORECLOCK != ((BASECLK / CLOCK_PLL_DIV) * CLOCK_PLL_MUL))
|
||||
#error "clock config: PLL configuration does not yield expected system clock"
|
||||
#endif
|
||||
/* make sure PLL_MUL is in range */
|
||||
#if (CLOCK_PLL_MUL < 2) || (CLOCK_PLL_MUL > 17)
|
||||
#error "clock config: CLOCK_PLL_MUL is out of range"
|
||||
#endif
|
||||
/* make sure PLL_DIV is 2 when using HSI as input */
|
||||
#if (!CLOCK_HSE) && (CLOCK_PLL_DIV != 2)
|
||||
#error "clock config: CLOCK_PLL_DIV must be 2 when using HSI oscillator"
|
||||
#endif
|
||||
/* and produce the actual PLL configuration */
|
||||
#if CLOCK_HSE
|
||||
#define PLLSRC (RCC_CFGR_PLLSRC)
|
||||
#if (CLOCK_PLL_DIV == 2)
|
||||
#define PLLDIV (RCC_CFGR_PLLXTPRE)
|
||||
#else
|
||||
#define PLLDIV (0)
|
||||
#endif
|
||||
#else
|
||||
#define PLLSRC (0)
|
||||
#define PLLDIV (0)
|
||||
#endif
|
||||
#define PLLMUL ((CLOCK_PLL_MUL - 2) << 18)
|
||||
/* and join it for writing the the CFGR register */
|
||||
#define PLLCFG (PLLMUL | PLLDIV | PLLSRC)
|
||||
#else
|
||||
#define PLLCFG (0)
|
||||
#endif
|
||||
|
||||
/* now we need to select the system clock source configuration */
|
||||
#ifdef USEPLL
|
||||
#define SYSCLK_SRC RCC_CFGR_SW_PLL
|
||||
#define SYSCLK_BSY RCC_CFGR_SWS_PLL
|
||||
#elif CLK_HSE
|
||||
#define SYSCLK_SRC RCC_CFGR_SW_HSE
|
||||
#define SYSCLK_BSY RCC_CFGR_SWS_HSE
|
||||
#elif
|
||||
#define SYSCLK_SRC RCC_CFGR_SW_HSI
|
||||
#define SYSCLK_BSY RCC_CFGR_SWS_HSI
|
||||
#endif
|
||||
|
||||
/* Configuration of flash access cycles */
|
||||
#define FLASH_WAITSTATES ((CLOCK_CORECLOCK - 1) / 24000000U)
|
||||
|
||||
/* define some bitfields */
|
||||
#define HSITRIM (1 << 7)
|
||||
#define SWSHSI (0)
|
||||
|
||||
|
||||
void stmclk_init_sysclk(void)
|
||||
{
|
||||
/* disable any IRQs */
|
||||
unsigned is = irq_disable();
|
||||
RCC->CIR = 0;
|
||||
|
||||
/* enable HSI and use it as system clock */
|
||||
stmclk_enable_hsi();
|
||||
RCC->CFGR &= ~(RCC_CFGR_SW);
|
||||
while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI) {}
|
||||
|
||||
/* its safe now to program the flash wait states */
|
||||
FLASH->ACR = (FLASH_ACR_PRFTBE | FLASH_WAITSTATES);
|
||||
/* now we are in a defined state and can stop all other clocks */
|
||||
RCC->CR = (HSITRIM | RCC_CR_HSION);
|
||||
/* next we put in the desired PLL and peripheral bus configuration */
|
||||
RCC->CFGR = (CLOCK_AHB_DIV | CLOCK_APB1_DIV | CLOCK_APB2_DIV | PLLCFG);
|
||||
|
||||
/* now we need to (re-)enable the used clocks */
|
||||
#if CLOCK_HSE
|
||||
RCC->CR |= RCC_CR_HSEON;
|
||||
while (!(RCC->CR & RCC_CR_HSERDY)) {}
|
||||
#endif
|
||||
#ifdef USEPLL
|
||||
RCC->CR |= RCC_CR_PLLON;
|
||||
while (!(RCC->CR & RCC_CR_PLLRDY)) {}
|
||||
#endif
|
||||
|
||||
/* leaves switching the system clock */
|
||||
RCC->CFGR |= SYSCLK_SRC;
|
||||
while ((RCC->CFGR & RCC_CFGR_SWS) != SYSCLK_BSY) {}
|
||||
|
||||
/* disable HSI (if not used) */
|
||||
stmclk_disable_hsi();
|
||||
|
||||
/* re-enable IRQs */
|
||||
irq_restore(is);
|
||||
}
|
||||
|
||||
void stmclk_enable_hsi(void)
|
||||
{
|
||||
RCC->CR |= RCC_CR_HSION;
|
||||
while (!(RCC->CR & RCC_CR_HSIRDY)) {}
|
||||
}
|
||||
|
||||
void stmclk_disable_hsi(void)
|
||||
{
|
||||
/* we only disable the HSI clock if not used as input for the PLL and if
|
||||
* not used directly as system clock */
|
||||
#ifdef CLOCK_HSE
|
||||
if ((RCC->CFGR & RCC_CFGR_SWS) != SWSHSI) {
|
||||
RCC->CR &= ~(RCC_CR_HSION);
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
void stmclk_enable_lfclk(void)
|
||||
{
|
||||
#if CLOCK_LSE
|
||||
stmclk_bdp_unlock();
|
||||
RCC->BDCR |= RCC_BDCR_LSEON;
|
||||
while (!(RCC->BDCR & RCC_BDCR_LSERDY)) {}
|
||||
stmclk_bdp_lock();
|
||||
#else
|
||||
RCC->CSR |= RCC_CSR_LSION;
|
||||
while (!(RCC->CSR & RCC_CSR_LSIRDY)) {}
|
||||
#endif
|
||||
}
|
||||
|
||||
void stmclk_disable_lfclk(void)
|
||||
{
|
||||
#if CLOCK_LSE
|
||||
stmclk_bdp_unlock();
|
||||
RCC->BDCR &= ~(RCC_BDCR_LSEON);
|
||||
stmclk_bdp_lock();
|
||||
#else
|
||||
RCC->CSR &= ~(RCC_CSR_LSION);
|
||||
#endif
|
||||
}
|
||||
|
||||
void stmclk_bdp_unlock(void)
|
||||
{
|
||||
periph_clk_en(APB1, RCC_APB1ENR_PWREN);
|
||||
PWR->CR |= PWR_CR_DBP;
|
||||
}
|
||||
|
||||
void stmclk_bdp_lock(void)
|
||||
{
|
||||
PWR->CR &= ~(PWR_CR_DBP);
|
||||
periph_clk_dis(APB1, RCC_APB1ENR_PWREN);
|
||||
}
|
||||
Loading…
Reference in New Issue
Block a user