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Merge pull request #3564 from haukepetersen/opt_f1_gpioaf

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cpu/stm32f1: simplified pin initialization in periph drivers
This commit is contained in:
Peter Kietzmann 2015-08-13 12:27:01 +02:00
commit c6d31aa507
6 changed files with 57 additions and 166 deletions
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34
boards/fox/include/periph_conf.h
View File

@ -94,11 +94,8 @@ extern "C" {
#define UART_0_ISR isr_usart2
#define UART_0_BUS_FREQ 36000000
/* UART 0 pin configuration */
#define UART_0_PORT GPIOA
#define UART_0_PORT_CLKEN() (RCC->APB2ENR |= RCC_APB2ENR_IOPAEN)
#define UART_0_RX_PIN 3
#define UART_0_TX_PIN 2
#define UART_0_AF 1
#define UART_0_RX_PIN GPIO(PORT_A,3)
#define UART_0_TX_PIN GPIO(PORT_A,2)
/* UART 1 device configuration */
#define UART_1_DEV USART1
@ -107,11 +104,8 @@ extern "C" {
#define UART_1_ISR isr_usart1
#define UART_1_BUS_FREQ 72000000
/* UART 1 pin configuration */
#define UART_1_PORT GPIOA
#define UART_1_PORT_CLKEN() (RCC->APB2ENR |= RCC_APB2ENR_IOPAEN)
#define UART_1_RX_PIN 10
#define UART_1_TX_PIN 9
#define UART_1_AF 0
#define UART_1_RX_PIN GPIO(PORT_A,10)
#define UART_1_TX_PIN GPIO(PORT_A,9)
/** @} */
/**
@ -127,15 +121,9 @@ extern "C" {
#define SPI_0_CLKDIS() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
#define SPI_0_BUS_DIV 0 /* 1 -> SPI runs with full CPU clock, 0 -> half CPU clock */
/* SPI 0 pin configuration */
#define SPI_0_CLK_PORT GPIOB
#define SPI_0_CLK_PIN 13
#define SPI_0_CLK_PORT_CLKEN() (RCC->APB2ENR |= RCC_APB2ENR_IOPBEN)
#define SPI_0_MOSI_PORT GPIOB
#define SPI_0_MOSI_PIN 15
#define SPI_0_MOSI_PORT_CLKEN() (RCC->APB2ENR |= RCC_APB2ENR_IOPBEN)
#define SPI_0_MISO_PORT GPIOB
#define SPI_0_MISO_PIN 14
#define SPI_0_MISO_PORT_CLKEN() (RCC->APB2ENR |= RCC_APB2ENR_IOPBEN)
#define SPI_0_CLK_PIN GPIO(PORT_B,13)
#define SPI_0_MOSI_PIN GPIO(PORT_B,15)
#define SPI_0_MISO_PIN GPIO(PORT_B,14)
/** @} */
/**
@ -171,12 +159,8 @@ extern "C" {
#define I2C_0_ERR_IRQ I2C1_ER_IRQn
#define I2C_0_ERR_ISR isr_i2c1_er
/* I2C 0 pin configuration */
#define I2C_0_SCL_PORT GPIOB
#define I2C_0_SCL_PIN 6
#define I2C_0_SCL_CLKEN() (RCC->APB2ENR |= RCC_APB2ENR_IOPBEN)
#define I2C_0_SDA_PORT GPIOB
#define I2C_0_SDA_PIN 7
#define I2C_0_SDA_CLKEN() (RCC->APB2ENR |= RCC_APB2ENR_IOPBEN)
#define I2C_0_SCL_PIN GPIO(PORT_B,6)
#define I2C_0_SDA_PIN GPIO(PORT_B,7)
/** @} */
#ifdef __cplusplus

34
boards/iot-lab_M3/include/periph_conf.h
View File

@ -95,11 +95,8 @@ extern "C" {
#define UART_0_ISR isr_usart1
#define UART_0_BUS_FREQ 72000000
/* UART 0 pin configuration */
#define UART_0_PORT GPIOA
#define UART_0_PORT_CLKEN() (RCC->APB2ENR |= RCC_APB2ENR_IOPAEN)
#define UART_0_RX_PIN 10
#define UART_0_TX_PIN 9
#define UART_0_AF 0
#define UART_0_RX_PIN GPIO(PORT_A,10)
#define UART_0_TX_PIN GPIO(PORT_A,9)
/* UART 1 device configuration */
#define UART_1_DEV USART2
@ -108,11 +105,8 @@ extern "C" {
#define UART_1_ISR isr_usart2
#define UART_1_BUS_FREQ 36000000
/* UART 1 pin configuration */
#define UART_1_PORT GPIOA
#define UART_1_PORT_CLKEN() (RCC->APB2ENR |= RCC_APB2ENR_IOPAEN)
#define UART_1_RX_PIN 3
#define UART_1_TX_PIN 2
#define UART_1_AF 1
#define UART_1_RX_PIN GPIO(PORT_A,3)
#define UART_1_TX_PIN GPIO(PORT_A,2)
/** @} */
/**
@ -128,15 +122,9 @@ extern "C" {
#define SPI_0_CLKDIS() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
#define SPI_0_BUS_DIV 1 /* 1 -> SPI runs with full CPU clock, 0 -> half CPU clock */
/* SPI 0 pin configuration */
#define SPI_0_CLK_PORT GPIOA
#define SPI_0_CLK_PIN 5
#define SPI_0_CLK_PORT_CLKEN() (RCC->APB2ENR |= RCC_APB2ENR_IOPAEN)
#define SPI_0_MOSI_PORT GPIOA
#define SPI_0_MOSI_PIN 7
#define SPI_0_MOSI_PORT_CLKEN() (RCC->APB2ENR |= RCC_APB2ENR_IOPAEN)
#define SPI_0_MISO_PORT GPIOA
#define SPI_0_MISO_PIN 6
#define SPI_0_MISO_PORT_CLKEN() (RCC->APB2ENR |= RCC_APB2ENR_IOPAEN)
#define SPI_0_CLK_PIN GPIO(PORT_A,5)
#define SPI_0_MOSI_PIN GPIO(PORT_A,7)
#define SPI_0_MISO_PIN GPIO(PORT_A,6)
/** @} */
/**
@ -172,12 +160,8 @@ extern "C" {
#define I2C_0_ERR_IRQ I2C1_ER_IRQn
#define I2C_0_ERR_ISR isr_i2c1_er
/* I2C 0 pin configuration */
#define I2C_0_SCL_PORT GPIOB
#define I2C_0_SCL_PIN 6
#define I2C_0_SCL_CLKEN() (RCC->APB2ENR |= RCC_APB2ENR_IOPBEN)
#define I2C_0_SDA_PORT GPIOB
#define I2C_0_SDA_PIN 7
#define I2C_0_SDA_CLKEN() (RCC->APB2ENR |= RCC_APB2ENR_IOPBEN)
#define I2C_0_SCL_PIN GPIO(PORT_B,6)
#define I2C_0_SDA_PIN GPIO(PORT_B,7)
/** @} */
#ifdef __cplusplus

19
boards/spark-core/include/periph_conf.h
View File

@ -93,11 +93,8 @@
#define UART_0_ISR isr_usart2
#define UART_0_BUS_FREQ (CLOCK_CORECLOCK/2)
/* UART 0 pin configuration */
#define UART_0_PORT GPIOA
#define UART_0_PORT_CLKEN() (RCC->APB2ENR |= RCC_APB2ENR_IOPAEN)
#define UART_0_RX_PIN 3
#define UART_0_TX_PIN 2
#define UART_0_AF 0
#define UART_0_RX_PIN GPIO(PORT_A,3)
#define UART_0_TX_PIN GPIO(PORT_A,2)
/** @} */
/**
@ -113,15 +110,9 @@
#define SPI_0_CLKDIS() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
#define SPI_0_BUS_DIV 0 /* 1 -> SPI runs with full CPU clock, 0 -> half CPU clock */
/* SPI 0 pin configuration */
#define SPI_0_CLK_PORT GPIOB
#define SPI_0_CLK_PIN 15
#define SPI_0_CLK_PORT_CLKEN() (RCC->APB2ENR |= RCC_APB2ENR_IOPBEN)
#define SPI_0_MOSI_PORT GPIOB
#define SPI_0_MOSI_PIN 17
#define SPI_0_MOSI_PORT_CLKEN() (RCC->APB2ENR |= RCC_APB2ENR_IOPBEN)
#define SPI_0_MISO_PORT GPIOB
#define SPI_0_MISO_PIN 16
#define SPI_0_MISO_PORT_CLKEN() (RCC->APB2ENR |= RCC_APB2ENR_IOPBEN)
#define SPI_0_CLK_PIN GPIO(PORT_B,15)
#define SPI_0_MOSI_PIN GPIO(PORT_B,17)
#define SPI_0_MISO_PIN GPIO(PORT_B,16)
/** @} */
#ifdef __cplusplus

78
cpu/stm32f1/periph/i2c.c
View File

@ -30,6 +30,7 @@
#include "mutex.h"
#include "periph_conf.h"
#include "periph/i2c.h"
#include "periph/gpio.h"
#define ENABLE_DEBUG (0)
#include "debug.h"
@ -39,8 +40,7 @@
/* static function definitions */
static void _i2c_init(I2C_TypeDef *i2c, int ccr);
static void _toggle_pins(GPIO_TypeDef *port_scl, GPIO_TypeDef *port_sda, int pin_scl, int pin_sda);
static void _pin_config(GPIO_TypeDef *port_scl, GPIO_TypeDef *port_sda, int pin_scl, int pin_sda);
static void _pin_config(gpio_t pin_scl, gpio_t pin_sda);
static void _start(I2C_TypeDef *dev, uint8_t address, uint8_t rw_flag);
static inline void _clear_addr(I2C_TypeDef *dev);
static inline void _write(I2C_TypeDef *dev, char *data, int length);
@ -67,9 +67,7 @@ static mutex_t locks[] = {
int i2c_init_master(i2c_t dev, i2c_speed_t speed)
{
I2C_TypeDef *i2c;
GPIO_TypeDef *port_scl;
GPIO_TypeDef *port_sda;
int pin_scl, pin_sda;
gpio_t pin_scl, pin_sda;
int ccr;
/* read speed configuration */
@ -89,13 +87,9 @@ int i2c_init_master(i2c_t dev, i2c_speed_t speed)
#if I2C_0_EN
case I2C_0:
i2c = I2C_0_DEV;
port_scl = I2C_0_SCL_PORT;
pin_scl = I2C_0_SCL_PIN;
port_sda = I2C_0_SDA_PORT;
pin_sda = I2C_0_SDA_PIN;
I2C_0_CLKEN();
I2C_0_SCL_CLKEN();
I2C_0_SDA_CLKEN();
NVIC_SetPriority(I2C_0_ERR_IRQ, I2C_IRQ_PRIO);
NVIC_EnableIRQ(I2C_0_ERR_IRQ);
break;
@ -105,8 +99,7 @@ int i2c_init_master(i2c_t dev, i2c_speed_t speed)
}
/* configure pins */
_pin_config(port_scl, port_sda, pin_scl, pin_sda);
_pin_config(pin_scl, pin_sda);
/* configure device */
_i2c_init(i2c, ccr);
@ -115,10 +108,8 @@ int i2c_init_master(i2c_t dev, i2c_speed_t speed)
DEBUG("LINE BUSY AFTER RESET -> toggle pins now\n");
/* disable peripheral */
i2c->CR1 &= ~I2C_CR1_PE;
/* toggle both pins to reset analog filter */
_toggle_pins(port_scl, port_sda, pin_scl, pin_sda);
/* reset pins for alternate function */
_pin_config(port_scl, port_sda, pin_scl, pin_sda);
/* re-run pin config to toggle and re-configure pins */
_pin_config(pin_scl, pin_sda);
/* make peripheral soft reset */
i2c->CR1 |= I2C_CR1_SWRST;
i2c->CR1 &= ~I2C_CR1_SWRST;
@ -143,49 +134,22 @@ static void _i2c_init(I2C_TypeDef *i2c, int ccr)
i2c->CR1 |= I2C_CR1_PE;
}
static void _pin_config(GPIO_TypeDef *port_scl, GPIO_TypeDef *port_sda, int pin_scl, int pin_sda)
static void _pin_config(gpio_t scl, gpio_t sda)
{
/* configure pins, alternate output, open-drain, output mode with 50MHz */
if (pin_scl < 8) {
port_scl->CR[0] |= (0xf << (pin_scl * 4));
}
else {
port_scl->CR[1] |= (0xf << ((pin_scl - 8) * 4));
}
if (pin_sda < 8) {
port_sda->CR[0] |= (0xf << (pin_sda * 4));
}
else {
port_sda->CR[1] |= (0xf << ((pin_sda - 8) * 4));
}
}
static void _toggle_pins(GPIO_TypeDef *port_scl, GPIO_TypeDef *port_sda, int pin_scl, int pin_sda)
{
/* configure pins, output, open-drain, output mode with 50MHz */
if (pin_scl < 8) {
port_scl->CR[0] |= (0x7 << (pin_scl * 4));
}
else {
port_scl->CR[1] |= (0x7 << ((pin_scl - 8) * 4));
}
if (pin_sda < 8) {
port_sda->CR[0] |= (0x7 << (pin_sda * 4));
}
else {
port_sda->CR[1] |= (0x7 << ((pin_sda - 8) * 4));
}
/* set both to high */
port_scl->ODR |= (1 << pin_scl);
port_sda->ODR |= (1 << pin_sda);
/* set SDA to low */
port_sda->ODR &= ~(1 << pin_sda);
/* set SCL to low */
port_scl->ODR &= ~(1 << pin_scl);
/* set SCL to high */
port_scl->ODR |= (1 << pin_scl);
/* set SDA to high */
port_sda->ODR |= (1 << pin_sda);
/* toggle pins to reset analog filter -> see datasheet */
/* set as output */
gpio_init(scl, GPIO_DIR_OUT, GPIO_NOPULL);
gpio_init(sda, GPIO_DIR_OUT, GPIO_NOPULL);
/* run through toggling sequence */
gpio_set(scl);
gpio_set(sda);
gpio_clear(sda);
gpio_clear(scl);
gpio_set(scl);
gpio_set(sda);
/* configure the pins alternate function */
gpio_init_af(scl, GPIO_AF_OUT_OD);
gpio_init_af(sda, GPIO_AF_OUT_OD);
}
int i2c_init_slave(i2c_t dev, uint8_t address)

27
cpu/stm32f1/periph/spi.c
View File

@ -109,18 +109,14 @@ int spi_init_slave(spi_t dev, spi_conf_t conf, char (*cb)(char))
int spi_conf_pins(spi_t dev)
{
GPIO_TypeDef *port[3];
int pin[3];
gpio_t mosi, miso, clk;
switch(dev) {
#ifdef SPI_0_EN
case SPI_0:
port[0] = SPI_0_CLK_PORT;
pin[0] = SPI_0_CLK_PIN;
port[1] = SPI_0_MOSI_PORT;
pin[1] = SPI_0_MOSI_PIN;
port[2] = SPI_0_MISO_PORT;
pin[2] = SPI_0_MISO_PIN;
clk = SPI_0_CLK_PIN;
mosi = SPI_0_MOSI_PIN;
miso = SPI_0_MISO_PIN;
break;
#endif
default:
@ -128,18 +124,9 @@ int spi_conf_pins(spi_t dev)
}
/* configure pins for alternate function input (MISO) or output (MOSI, CLK) */
for (int i = 0; i < 3; i++) {
int crbitval = (i < 2) ? 0xb : 0x4;
if (pin[i] < 8) {
port[i]->CR[0] &= ~(0xf << (pin[i] * 4));
port[i]->CR[0] |= (crbitval << (pin[i] * 4));
}
else {
port[i]->CR[1] &= ~(0xf << ((pin[i] - 8) * 4));
port[i]->CR[1] |= (crbitval << ((pin[i] - 8) * 4));
}
}
gpio_init_af(clk, GPIO_AF_OUT_PP);
gpio_init_af(mosi, GPIO_AF_OUT_PP);
gpio_init(miso, GPIO_DIR_IN, GPIO_NOPULL);
return 0;
}

31
cpu/stm32f1/periph/uart.c
View File

@ -25,6 +25,7 @@
#include "board.h"
#include "periph_conf.h"
#include "periph/uart.h"
#include "periph/gpio.h"
#include "sched.h"
#include "thread.h"
@ -99,8 +100,8 @@ int uart_init(uart_t uart, uint32_t baudrate, uart_rx_cb_t rx_cb,
int uart_init_blocking(uart_t uart, uint32_t baudrate)
{
USART_TypeDef *dev;
GPIO_TypeDef *port;
uint32_t rx_pin, tx_pin, bus_freq;
uint32_t bus_freq;
gpio_t rx_pin, tx_pin;
float divider;
uint16_t mantissa;
uint8_t fraction;
@ -110,48 +111,29 @@ int uart_init_blocking(uart_t uart, uint32_t baudrate)
#if UART_0_EN
case UART_0:
dev = UART_0_DEV;
port = UART_0_PORT;
rx_pin = UART_0_RX_PIN;
tx_pin = UART_0_TX_PIN;
bus_freq = UART_0_BUS_FREQ;
/* enable clocks */
UART_0_CLKEN();
UART_0_PORT_CLKEN();
break;
#endif
#if UART_1_EN
case UART_1:
dev = UART_1_DEV;
port = UART_1_PORT;
tx_pin = UART_1_TX_PIN;
rx_pin = UART_1_RX_PIN;
bus_freq = UART_1_BUS_FREQ;
/* enable clocks */
UART_1_CLKEN();
UART_1_PORT_CLKEN();
break;
#endif
default:
return -2;
}
/* Configure USART Tx as alternate function push-pull and 50MHz*/
if (tx_pin < 8) {
port->CR[0] &= ~(0xf << (tx_pin * 4));
port->CR[0] |= (0xB << (tx_pin * 4));
}
else {
port->CR[1] &= ~(0xf << ((tx_pin-8) * 4));
port->CR[1] |= (0xB << ((tx_pin-8) * 4));
}
/* Configure USART Rx as floating input */
if (rx_pin < 8) {
port->CR[0] &= ~(0xf << (rx_pin * 4));
port->CR[0] |= (0x4 << (rx_pin * 4));
}
else {
port->CR[1] &= ~(0xf << ((rx_pin-8) * 4));
port->CR[1] |= (0x4 << ((rx_pin-8) * 4));
}
/* configure RX and TX pin */
gpio_init_af(tx_pin, GPIO_AF_OUT_PP);
gpio_init(rx_pin, GPIO_DIR_IN, GPIO_NOPULL);
/* configure UART to mode 8N1 with given baudrate */
divider = ((float)bus_freq) / (16 * baudrate);
@ -162,7 +144,6 @@ int uart_init_blocking(uart_t uart, uint32_t baudrate)
/* enable receive and transmit mode */
dev->CR1 |= USART_CR1_UE | USART_CR1_TE | USART_CR1_RE;
return 0;
}